timer equivalent for "DC " analysis for verilog-a

The @(cross...) is purely for time-domain events, but you can use @(above(...)) - for example:

@(above(V(p,n))) begin
  $strobe("ABOVE = ",V(p,n));
end

above(x <, timetol <, abstol <, enable >>>)

Generates an event when 'x' becomes greater than or equal to zero. An above event can be generated and detected during initialization. By contrast, a cross event can be generated and detected only after at least one transient time step is complete.

So it's not quite what you're asking, but may be sufficient for the DC case at least. In a dc sweep the above will trigger as the x expression becomes positive. In general Verilog-A models should be written to operate in the time-domain and you should not try to write different behaviour for different analyses. In an ac analysis, the equations described in the VerilogA model are linearised and then simulated in the small-signal AC analysis. It does not then execute the code during the AC as it's simulating the small-signal linear model instead, and so you cannot have something that is triggered at a particular frequency - it makes no sense in VerilogA.

Regards,

Andrew.