Design a 2nd order digital delta-sigma modulator

Dear Archin2019.

Dear Archin2019,

Archon2019 said:

If the input is a 16-bit digital signal, and assume that the word length of integrators is enough so that overflow is avoid, then 

1) will the precision change when I add more bits?

2) will the quantization increase when I add more bits?

I may be misunderstanding your questions as I don't fully understand your design. You note the "input" is a 16-bit digital signal. Usually, the input is an analog signal that is oversampled and followed by a delta-sigma modulator. Is this what you mean - or are you just referring to the integrator word lengths in the delta-sigma?

If the case is the latter, the quantization noise is set by the oversampling ratio and the order of the delta-sigma. Specifically, the sample frequency determines the bandwidth over which the quantization noise is spread and the order of the delta-sigma determines the portion of this band that is not filtered out. Hence, if you do not have sufficient resolution in your integrators ( i.e., "bits" as you refer to them), this will only serve to provide a less than perfect integration and hence increase the quantization noise beyond its theoretical value for a given oversampling ratio and delta-sigma order.

I hope I understood a bit of your question Archin2019 and this helps with your intuition. These types of systems and their word sizes are validated in simulations.

Shawn

Dear Shawn,

Sorry for the confusion. 

The delta-sigma modulator is a digital delta-sigma modulator used in a fractional-N PLL. The input is a 16-bit digital signal controlling the division ratio, and all internal signals are digital signals.

(I think you are talking about analog delta-sigma, which is usually used in a delta-sigma ADC)

In this case, if we assume integrators have B-bit and overflow is avoid. Then if we add several bits, say (B+1)-bit or (B+5)-bit, will this reduce the quantization noise of the digital delta-sigma modulator?

I found some figures from Internet to show the design.

Thanks a lot for your help!

Dear Archon2019,

Thank you for your more detailed explanation - it is quite useful!

Archon2019 said:

In this case, if we assume integrators have B-bit and overflow is avoid. Then if we add several bits, say (B+1)-bit or (B+5)-bit, will this reduce the quantization noise of the digital delta-sigma modulator?

I will let other experts comment, but I believe my original response may still be the answer. In short, as you increase the number of bits used in integrator 1 or integrator 2, you are only reducing the error of the two integration operations - not the fundamental quantization noise of the delta-signal modulator. Put another way, suppose you only used a couple of bits in each of the two integrators. As a result, their integrator operations will not be perform like "ideal integrators" and hence will definitely add more noise to your modulator. AS you increase the number of bits used in each integrator, you are simply making each integration operation act closed to an "ideal integrator" and the quantization noise of the modulator will be closer to that determined by its order and oversampling.

Do you agree?

Shawn