Stats

  • Locked Locked
  • Replies 6
  • Subscribers 64
  • Views 18741
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Simulate frequency response of behavioral digital filter

pepijndevos

I am making a system with a sigma delta modulator, which for reasons that are not relevant now, has a IIR decimation filter.

My supervisors recommended that I try writing it in veriloga rather than VHDL-AMS, so that I can keep using Spectre rather than a full AMS simulation.

So I wrote the below second order section that I hope to combine into higher order filters guided by Matlab filter design tools.

// VerilogA for zerogain, sos, veriloga

`include "constants.vams"
`include "disciplines.vams"

module sos(vin, vout, vclk);
input vin,vclk;
output vout;
electrical vin, vout, vclk;

parameter real vtrans_clk = 0.6;
parameter real B0=1;
parameter real B1=0;
parameter real B2=0;
parameter real A1=0;
parameter real A2=0;
parameter real tdel = 0 from [0:inf);
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);

   real vin_val, vinz1, vinz2;
   real vout_val, voutz1, voutz2;

   analog begin
      @ (cross(V(vclk) - vtrans_clk, 1)) begin
         vinz2 = vinz1;
         vinz1 = vin_val;
         vin_val = V(vin);
         voutz2 = voutz1;
         voutz1 = vout_val;
         vout_val = (vin_val*B0 + vinz1*B1 + vinz2*B2)/(1 + voutz1*A1 + voutz2*A2);
      end
      V(vout) <+ transition(vout_val,tdel,trise,tfall);
   end
endmodule

However, I'm having some trouble simulating it. Inside my sigma-delta loop the output is mere microvolt, for a 100mV input signal.

So I figured I should make a proper testbench for this model. Of course I'm primarily interested in the frequency behavior, but it is not a LTI system.

I figured I might be able to do a pss/pac analysis, but this throws an error about hidden internal state.

As an alternative, I thought I could sweep a sine through it, but I could not find an easy way to do that, it does not appear that the tran simulation has a parameter sweep option.

Of course I did do a normal transient simulation, which works somewhat better than my full system, but it's hard to debug the system. Is there a way to plot the internal variables of the veriloga module?

  • ShawnLogan

    Dear pepijndevos,

    pepijndevos said:
    Is there a way to plot the internal variables of the veriloga module?

    There is a procedure outlined at URL:

    support.cadence.com/.../ArticleAttachmentPortal

    that illustrates a method to save internal variables of a veriloga block.  Did you examine this to see if it might satisfy your need? It appears to be exactly what you might want to study an internal voltage (or signal) inside your sos() module.

    pepijndevos said:
    As an alternative, I thought I could sweep a sine through it, but I could not find an easy way to do that, it does not appear that the tran simulation has a parameter sweep option.

    From my limited understanding of your objective, if you are trying to sweep the input frequency over a range to characterize the frequency response of your sigma-delta based  modulator (i.e., each unique input frequency will provide an output corresponding to the response at that frequency), this is possible with Assembler (or the former ADE-XL). The input frequency of the sinusoid is assigned to a variable and the the variable is swept over a range of values to your choosing. Assembler will run a set of simulations at each frequency. If you assigned the ratio of output amplitude to input amplitude (over a narrow band about each frequency value to avoid noise impacting your result), as an output expression, this will provide the transfer function of your sigma-delta modulator.

    I hope my understanding of your issues is somewhat correct and  the suggestions help a bit anyway!

    Shawn

  • Andrew Beckett
    in reply to ShawnLogan

    The article that Shawn mentioned (which was written by me, as it happens) is talking about how to selectively save some of the internal variables inside VerilogA modules. If you don't have too many internal variables to save (i.e. there are relatively few VerilogA blocks in the design), you could simply go to Outputs->Save All and set the saveahdlvars setting to all. You can then access the variable values inside the tran database in the Results browser to plot them. I thought I'd mention this in case you're at an academic institution and don't have Cadence Online Support access easily available (it should be available, but it may not have been set up for you). I won't go through the detail of doing this selectively as that will take too long - and better just to look at the article - but as a quick fix maybe saving all internal variables would suffice.

    Regards,

    Andrew.

  • pepijndevos
    in reply to Andrew Beckett

    Indeed I have no host ID from my university to access the mentioned article. I might be able to find out, but yea... for my simple testbench saving all variables seems like the way to go. Thanks.

  • pepijndevos
    in reply to ShawnLogan

    So after a long struggle, I redesigned my system to not have internal states. However, I'm hoping you could tell me a bit more about sweeping transient solutions? I opened ADE-XL and could not really make sense of it. I managed to run a regular ADE L simulation with it, but not sweep anything. I can also not figure out how to use the calculator in ADE-L to find the magnitude of a particular frequency as a scalar number.

  • ShawnLogan
    in reply to pepijndevos

    Dear pepijndevos,

    pepijndevos said:
    However, I'm hoping you could tell me a bit more about sweeping transient solutions? I opened ADE-XL and could not really make sense of it. I managed to run a regular ADE L simulation with it, but not sweep anything. I can also not figure out how to use the calculator in ADE-L to find the magnitude of a particular frequency as a scalar number.

    There is a lot of information readily available on sweeping transient simulations. First, if you have not used ADE-XL before, I would recommend jumping to ADE Assembler as that is the more recent incarnation of ADE-XL and the latter is not actively being supported. Without a specific goal and very detailed circuit information, it would not be feasible for me to repeat much of the documentation in my response to you. I might recommend you start your study with the following:

    https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000006DeuPUAS&pageName=ArticleContent

    Shawn

  • pepijndevos
    in reply to ShawnLogan

    Thanks, I will ask my university about a host ID or reference to access this material.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.