How to include Verilog functional files in Virtuoso Hierarchy Editor for SDF Simulation

Hello,

I am using config view AMS simulator to simulate analog CMOS amplifier in schematics view with Verilog functional code.

I am able to simulate RTL level just fine, but I don't know how to annotate the devices with SDF file to include maximum or minimum delays to my code.

Let me explain my setup below:

In RTL level simulation (In Cadence):

 - I normally have multiple separate verilog files for each module added to separate verilog cells. The top cell verilog calls all other modules inside the top level code. I place the top level verilog cell symbol along with my amplifier in schematics.

 - Then I adjust the connect rules and do an AMS simulation.

In GATE level simulation (In NCVerilog Not Cadence):

 - I am able to emulate the GATE-level simulation by adding delays annotated from an SDF file in ncverilog only.

 - The synthesizer outputs 1 huge file with all modules written in one file. I can use this file in my verilog test bench in ncverilog as shown:

    //`include "/full_rtl_lib_path/DIGITAL_MODULE.v"      // uncomment this line for RTL

    `include "/full_gate_lib_path/DIGITAL_MODULE_top_sim.v"      // This is a one huge file that includes all synthesized modules
    `include "/full_pdk_path/verilog/sc9_cln65lp_base_hvt.v"           // Includes gate delays
    `include "/full_pdk_path/verilog/sc9_cln65lp_base_hvt_udp.v"   // Includes gate delays

     ..

     initial begin

          $sdf_annotate("/full_gate_lib_path/DIGITAL_MODULE_apr.sdf", DIGITAL_MODULE_TB.tdma_transceiver_module, , ,"maximum");

    end

    ..

   // The rest of the test bench code is written here

- Then I run ncverilog, and the delays get included.

Since it is very hard to simulate actual CMOS gate-level simulation in Cadence AMS (I have over 1M device), I want to apply the same NCVerilog technique in AMS simulator but I have three question:

1) How can I include the above verilog files given that I have one huge file with the top digital module + the rest of the modules? (P.S.: The synthesized modules are over 100 modules, so it is hard to copy each in a separate verilog cell)

2) How do I include the SDF file to emulate the maximum or minimum delays?

3) How do I include the verilog libraries of my PDK in the AMS hierarchy editor?

If I copied all "DIGITAL_MODULE_top_sim.v" into a verilog file, in the config view the hierarchy editor recognizes the top module only and doesn't recognize any of the other modules defined in the file.

Any help is much appreciated!

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9

Many thanks in advance!

Kindest Regards,

Nader Sh.