I am doing a simulation in Cadence for a Delta-Sigma ADC with blocks like op-amp and Quantizer modeled in Verilog-A environment. The quantizer is a single-bit quantizer and hence modelled just as a comparator that works on a clock with V(out) = +1 when the V(in) > 0 and V(out) = -1 when the V(in) < 0. In the quantizer block, I have a code piece that does a file export in .dat format (@filecheck (path of the destination to store the file)). This is performed because I will load this file generated into Matlab and verify the performance metrics like SNR and IBN through the code run in Matlab.
Now I want to sweep that amplitude lets say for 100 levels between a minimum and maximum. With this, I would like to generate 100 file outputs on each iteration such that I can load that in Matlab using an iteration of 100 levels.
How can I modify the Verilog-A code so as to generate each file at each amplitude iteration without just replacing the existing file each time?
Below is the current code: