I am pretty new to Cadence AMS simulator. I am trying to simulate verilog and verilog-A described blocks in a test-bench but while I net-listing receive this error that verilog-A block ports are not found.
`I45': An instance of `resistor', port name `t2' not found.
However when I check the netlist.vams file the blocks net list seems fine : "resistor #(.r(1)) I45 (.t2( vdd ), .t1(cds_globals.\gnd! ));"
I would be thankful if anybody can say what is the cause of the error.
I get this error if I run in the obsolete "Cellview-based netlister" mode (on Simulation->Netlist and Run options) if I have a VerilogA module which matches a spectre primitive (which is not really allowed). The issue here is that resistor is a primitive in spectre, and whilst spectre does allow redefinition of Spectre primitives with a VerilogA model, AMS doesn't. In the old CBN netlister that you're using (which is no longer there in IC618 - only Unified Netlister ,UNL is available now), you get:
Fatal error found by spectre in `mylib__restb__schematic__0x10000001', during circuit read-in. FATAL (SFE-82): "/export/home/andrewb/simulation/mylib/restb/maestro/results/maestro/ExplorerRun.0/1/RESTB_AMS/netlist/ihnl/mylib/restb/schematic/verilog.vams" 16: `I1': An instance of `resistor', port name `t1' not found.
If you pick the UNL netlister, it gives this during simulation:
ncelab: *F,OSSPBT: 'restb.I1' of cell 'resistor' is a SPICE built-in primitive. It cannot be configured to another view like 'External HDL' via Cadence Hierarchy Editor.
I would suggest that you call your VerilogA resistor something other than "resistor", and then it should work.
By the way, when making posts like this, it's always best to mention the software versions you're using (the IC version and the simulator version), as that helps narrow down any issues.
Thank you so much for the reply, I changing the name and it did the work! Also my software version is IC6.1.8.
However in my simulation I also have a .cir described block and I get the same error for this block too:
147: `I47': An instance of `ADA4528', port name `VSS' not found.
Is this again a name problem or AMS doesn't work with .cir blocks?
I also changed the name of the block model "ADA4528" and the problem resolved! Thank you so much for the help.
I don't really understand why this would need renaming, and I don't know what you mean by ".cir" blocks, but hey ho, you've got it working now...
The .cir block is an opamp that is described with a spice model .cir. and is not schematic or verilog A model.