We use the command line flow(spicetop) for mixed-signal verification.
For speeding up the sims, we need to have functional views(verilog) for some portion of the analog circuit. The number of analog components which needs to use 'HDL' view is ~50-100. Writing the amscf.scs file with individual portmaps is taking a lot of time.
Is there an automated way to generate amscf.scs like the way we do using hierarchy editor?