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coupling between digital outputs in cosim?

DavidLou
hello experts,
some interesting phenomenon noticed from mix-signal cosim and I'm wondering how can I manipulate that. I have  digital bus output through connect_lib/L2E_1 and become analog signals.a couple bits of the bus toggles as shown in the waveform from low (0V) to high (5V). consequently all the other static bits get interference, e.g., out[2]/diff_p could swing from 5V to 5.05V. such 50mV swing in very short time (0.2ns) could make following inverter to swing up from 0V to 700mV+ which is high enough to turn on transistors unintentionally and causing misbehavior or leakage. 
so my questions are: where and how is such interference between digital outputs defined, e.g., how much coupling capacitance between, in what spacing order, pattern, etc.? and how do we confirm it's realistic or not?
P.S., cosim with Xcelium 18.03-s017 and IC6.1.7-CAT35
thanks,
David

  • Dear David,

    DavidLou said:
    so my questions are: where and how is such interference between digital outputs defined, e.g., how much coupling capacitance between, in what spacing order, pattern, etc.? and how do we confirm it's realistic or not?

    1. I would be amazed if a 50 mV noise pulse due to coupling causes a 5V based logic gate to change its output logic state. The threshold of a 5V based CMOS inverter is going to be on the order 2.5 V and hence its gain will be a maximum near this DC value. At a DC level of 5V, its gain will be very small and hence I would not think a 50 mV noise signal will result in any type of output transition. Am I overlooking something in the results you are providing to us?

    2. Unless it is associated with your timing setup for your simulation, the 50 mV noise signals you show are not coincident with the aggressor signals you have highlighted at 1000 ns. If the mechanism is capacitive coupling the resulting noise will be nearly coincident with the transition of the aggressor signal(s). Are there any signals whose transitions are closer to the 50 mV noise signals that are displayed?

    3. There is no specific value of coupling capacitance that is always acceptable. The amount that is acceptable depends on the technology and the aggressor signal characteristics. Hence, I, for one, cannot provide a "rule of thumb" value that is always "acceptable".

    My apologies, David, if I am overlooking something about your plot or your questions.

    Shawn

  • in reply to ShawnLogan

    Hi Shawn, yup, turns out you are absolutely right. it's something else causing such interference, not digital at all.

    thanks,

    David

  • in reply to DavidLou

    Dear DavidLou,

    DavidLou said:
    t's something else causing such interference, not digital at all.

    Thank you for letting us know! Good luck debugging this issue - these things can be insidious and hope you find the answer soon.

    Shawn

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