I have a low-frequency low-power ADC design to simulate dynamic performance with an sine wave input. In order to make a meaningful FFT transformation, the simulation time is set to be long (a few seconds) to get enough FFT data points. However, the simulation failed at the same point several times with a message: "Unexpected signal #25 (File Size Limit Exceed), program terminated. "
I have tried Xcelium 18 and Xcelium 19. Both are the same. The analogue part of the simulation uses APS. In the NC-Verilog documentation menual (not Xcelium), there is a section saying that NC-verilog has a limit of file size around 2GB due to 32-bit OS, which an be overwritten with a custom tcl script. However I am using 64-bit OS, and this is xmvlog instead of ncvlog. The CDS_AUTO_64BIT variable has been set to 'ALL', and the log file indicates that all executables involved are 64-bit. The result file tran.tran.tran in the psf directory is indeed 2.049 GB when it stops.
I wonder if there is any option setting that can overcome this limit? Thanks in advance.