Create an array of variables using an array of vdc instances

Dear jdimov,

jdimov said:

At this point what would be very neat is to be able to enter vh<0:3> as a design variable for the DC voltage value, as you can see in the bottom left corner in the Property Editor tab of the V5<0:3> generator array.

If I understand your question correctly, I made a simple 8 bit veriloga "A/D" converter to create a digital bus whose decimal value is a design variable. Figure 1 shows the instantiation of the 8 bit veriloga symbol. A pulse generator that takes two design values drives the A/D input input and toggles between two decimal values that are converted to their respective 8 bit binary words. You can leave any unused bits of the converter as no connects to create an N bit bus where N<8. You could also drive it with a DC source whose value is set as a single design variable.

I've included the code for the cell from which you can create a symbol for use in schematics. I hope this provides some insight to you - assuming I correctly understood your question!

Shawn

Fiigure 1

Example if instantiation of 8 bit veriloga based A/D

Dear jdimov,

jdimov said:

At this point what would be very neat is to be able to enter vh<0:3> as a design variable for the DC voltage value, as you can see in the bottom left corner in the Property Editor tab of the V5<0:3> generator array.

If I understand your question correctly, I made a simple 8 bit veriloga "A/D" converter to create a digital bus whose decimal value is a design variable. Figure 1 shows the instantiation of the 8 bit veriloga symbol. A pulse generator that takes two design values drives the A/D input input and toggles between two decimal values that are converted to their respective 8 bit binary words. You can leave any unused bits of the converter as no connects to create an N bit bus where N<8. You could also drive it with a DC source whose value is set as a single design variable.

I've included the code for the cell from which you can create a symbol for use in schematics. I hope this provides some insight to you - assuming I correctly understood your question!

Shawn

Fiigure 1

Example if instantiation of 8 bit veriloga based A/D

// VerilogA for simple transient compatible eightbit_ad,
// sml 8/10/2020

`include "constants.vams"
`include "disciplines.vams"

module eightbit_ad(VOUT, VDD, VIN, VSS);
output [7:0] VOUT;
electrical [7:0] VOUT;
input VDD;
electrical VDD;
input VIN;
electrical VIN;
input VSS;
electrical VSS;
integer vin_integer;
parameter real rise_fall_time = 50e-12;
integer vout[7:0];

analog begin

vin_integer = V(VIN,VSS);

if (vin_integer%256<128) V(VOUT[7],VSS)<+V(VSS);
else V(VOUT[7],VSS)<+V(VDD,VSS);
V(VOUT[7],VSS)<+ transition(V(VDD)*vout[7],rise_fall_time,rise_fall_time);

if (vin_integer%128<64) V(VOUT[6],VSS)<+V(VSS);
else V(VOUT[6],VSS)<+V(VDD,VSS);
V(VOUT[6],VSS)<+ transition(V(VDD)*vout[6],rise_fall_time,rise_fall_time);

if (vin_integer%64<32) V(VOUT[5],VSS)<+V(VSS);
else V(VOUT[5],VSS)<+V(VDD,VSS);
V(VOUT[5],VSS)<+ transition(V(VDD)*vout[5],rise_fall_time,rise_fall_time);

if (vin_integer%32<16) V(VOUT[4],VSS)<+V(VSS);
else V(VOUT[4],VSS)<+V(VDD,VSS);
V(VOUT[4],VSS)<+ transition(V(VDD)*vout[4],rise_fall_time,rise_fall_time);

if (vin_integer%16<8) V(VOUT[3],VSS)<+V(VSS);
else V(VOUT[3],VSS)<+V(VDD,VSS);
V(VOUT[3],VSS)<+ transition(V(VDD)*vout[3],rise_fall_time,rise_fall_time);

if (vin_integer%8<4) V(VOUT[2],VSS)<+V(VSS);
else V(VOUT[2],VSS)<+V(VDD,VSS);
V(VOUT[2],VSS)<+ transition(V(VDD)*vout[2],rise_fall_time,rise_fall_time);

if (vin_integer%4<2) vout[1]=0;
else vout[1]=1;
V(VOUT[1],VSS)<+ transition(V(VDD)*vout[1],rise_fall_time,rise_fall_time);

if (vin_integer%2<1) vout[0]=0;
else vout[0]=1;
V(VOUT[0],VSS)<+ transition(V(VDD)*vout[0],rise_fall_time,rise_fall_time);

end

endmodule

Hi ShawnLogan and thanks for a detailed reply. I think I understood your ADC but I am not it corresponds to my question so I'll try to explain it more.

My question is more discussion based.

For a scenario in which you have a top-level chip to test and it has both analog and digital inputs, various, and let's say all in all you have to create 40 input signals and many are buses with bits you need to change from test to test. And you will be using ADE to create your testbench schematic. (and don't limit yourself to transient simulation only, you use these for dc simulations too)

What would be your approach to creating the 40 signals? (in ADE)

Through my experience there were times I would create those 40 vdc (or some vbit, vpulse) generators by hand, then go into labeling them...
My other approach was to create a verilogams module with simple output structure with what I needed and then instantiate that cellview with its symbol, etc. .... but this was not favorable with other team members for example. Many preferred to see the generators for different reasons.

Thinking about ways to make the process of creating this kind of testbench quicker I was hoping (for cases where you need to input bus/vector signals) to instantiate an array of vdc generators (the left side of my picture) like V5<0:3> and hoped that if I enter a design variable for DC voltage value like "vh<0:3>" that it would create 4 different design variables in ADE. It didn't. I don't know if that is even possible or not. If it's possible maybe I'm not doing it right then...?

A couple of other ideas:

1. Use the "bussetp" component I created from this article: Creating a component that allows setting a value on a bus in an analog simulation
2. Use a vector file (Setup->Simulation Files in ADE) to allow you to create stimulus based on a vector file input. That tends to be more useful if you want time-varying values rather than static values.

Andrew

A couple of other ideas:

1. Use the "bussetp" component I created from this article: Creating a component that allows setting a value on a bus in an analog simulation
2. Use a vector file (Setup->Simulation Files in ADE) to allow you to create stimulus based on a vector file input. That tends to be more useful if you want time-varying values rather than static values.

Andrew

Hi Andrey,

The bussetp component is really helpful!

I never used vector files. I found some documentation about it so I'll have to look into it a bit more.

Thanks