Simulation of period jitter of a relaxation oscillator

Dear Martin,

Unknown said:

I have some questions related to the simulation of period jitter of a relaxation oscillator. The oscillator is running at around 8 MHz and produces a digital output signal. Flicker noise is the dominating noise source in the design.

Are you really interested in period jitter as opposed to random phase jitter for your relaxation oscillator? It seems to me the latter is the more relevant given your desire to compute the rms jitter from 100 kHz to 100 MHz. It seems to me that using the time-averaged methodology is more consistent with your end expecation. The time-average of the noise at the output of the circuit is computed in the form of  spectral density versus frequency - from which you can compute the phase jitter over any frequency band you are interested.

The reference for submitting phase noise simulations may be found at URL:

https://support.cadence.com/apex/techpubDocViewerPage?path=spectreRFinExplorer/spectreRFinExplorer19.1/Chap4.html#pnoise

Unknown said:

To calculate the RMS jitter, I have to set the integration limits. I chose 100Hz to 100MHz. But if I set the integration start frequency to a higher frequency (e.g. 1kHz) the calculated RMS jitter is higher. This is not intuitive to me. Why do I get this behavior?

I suspect you have not set up your simulation to accurately capture the noise components at low frequencies - either insufficient frequency points or the tstab is not long enough to accurately estimate the periodic components that low in frequency. Unless you are dealing with very high precision oscillators (quartz based or even higher Q), the phase noise components less than 10 kHz or so are not relevant. Most integrated VCO are used in phase-locked loops whose bandwidths will ensure that VCO noise components less than 10 KHz are attenuated significantly. The output phase noise at those low offset frequencies will appear similar to the reference clock phase noise driving the phase-locked loop - not that of your VCO. There are tpp many details concerning your simulation and circuit for me to provide any good insight as to exactly why you are experiencing that result - sorry!

Unknown said:

It seems that I get more accurate results when I choose linear steps for pnoise instead of logarithmic steps. The higher the number of steps, the better the modelling of the slopes of the harmonics. When increasing the number of steps, the calculated RMS jitter reduces a little bit for k=1 (ok, better approximations of slopes), but the RMS jitter for k=512 increases significantly. I don't understand why

This makes no sense to me Martin. I honestly think your analysis setup is not correct. In fact, I'm not sure I understand your comment "The higher the number of steps, the better the modeling of the slopes of the harmonics."

Perhaps if you consider running a time averaged pnoise analysis and look over the section of the manual I provided to choose your settings for your application, your results will be both more intuitive and in line with measured data.

Shawn

Hi Shawn,

thanks for your response and the shared link. For some reason I did not find it before. But the instructions confirmed me in my oppinion in the setup.

ShawnLogan said:

Are you really interested in period jitter as opposed to random phase jitter for your relaxation oscillator?

Yes, I'm interested in period jitter, because we measured this type of jitter with a scope in the transient domain. I'd like to match simulation and measurement results. My problem is, that the simulated amount of jitter largely depends on the simulation setup. Compared to that, the difference of certain jitter types is almost negligible.

However, I believe that the measurement of period jitter goes in the right direction. In my application, the oscillator is a free-running oscillator serving as the master clock for a PWM-like output protocol. I have a specification for the RMS jitter of the longest output pulse on system level. The longest pulse is generated by the sum of several successive pulses of the master clock. The spec is not very precise for the jitter definition. In addition, we have also synchronization of the receiver to the pulses. This means that low frequency noise of the oscillator does not need to be taken into account.

ShawnLogan said:

There are tpp many details concerning your simulation and circuit for me to provide any good insight as to exactly why you are experiencing that result - sorry!

This is a rough description of the oscillator architecture: A current is generated from a reference voltage and a resistor. The current is mirrored and injected to a cap. The cap is charged unless its voltage reaches the comparator threshold. This threshold has a fixed ratio to the reference voltage. The oscillator frequency depends on the time constant of resistor and cap. Main noise sources are flicker noise in the CMOS current mirrors and the CMOS comparator. The oscillator core behaves like a saw-tooth generator, the comparator rectifies the signal.

After spending more time on the topic, this is my understanding: The oscillator is dominated by low frequency noise. This noise is mixed up to each harmonic because of the rectification process. Measuring the integrated noise in the frequency domain would only make sense, if I would neglect the up-converted low frequency noise at each harmonic.

ShawnLogan said:

Perhaps if you consider running a time averaged pnoise analysis and look over the section of the manual I provided to choose your settings for your application, your results will be both more intuitive and in line with measured data.

I tried time averaged pnoise too. The sensitivity to the simulation setup is comparable, but the RMS jitter value is higher compared to sampled time or lab measurements.

All in all I'm not sure if pnoise is well suited for my circuit because of the rectification inside the oscillator. Small noise amplitudes may cause large differences in the output signal. What is your opinion? 

Regards, Martin

Dear Martin,

Thank you, very much, for the added information concerning your application, the requirement you are tackling, and the oscillator architecture. All are extremely helpful, for me anyway, to better understand your original concerns!

Martin Schmidt said:

I have a specification for the RMS jitter of the longest output pulse on system level. The longest pulse is generated by the sum of several successive pulses of the master clock. The spec is not very precise for the jitter definition. In addition, we have also synchronization of the receiver to the pulses. This means that low frequency noise of the oscillator does not need to be taken into account.

It sounds to me as if your specification may not be a period jitter related entity, but rather an N cycle jitter measurement where N is the maximum number of oscillator periods that form your "longest pulse". There are relationships between a cycle-to-cycle jitter measurement, a period jitter measurement and a phase noise measurement that basically high-pass and weight the phase noise characteristic. Hence, one could use a pnoise time-averaged characteristic to estimate the N cycle jitter rms value. However, in thinking about your specific requirement and objective, here is how I might consider approaching estimating the rms N cycle jitter.

1. Assuming you know the maximum number of successive periods of your oscillator output that form the "longest output pulse on system level", I would include an ideal frequency divider (i.e., noiseless) following your relaxation oscillator. Hence, the cycle-to-cycle time variation of the divider output represents the jitter of your "longest output pulse on system level". 

2. Perform a pss/pnose (sampled-jitter) analysis where the frequency is governed by, not the fundamental frequency of your relaxation oscillator, but rather its divided output. Some hints on performing a pss/pnoise simulation on a netlist with frequency dividers is provided at URL:

Guidelines for simulating frequency dividers in Spectre RF

3. Compute the Jcc for your divided relaxation oscillator output from the Direct Plot form following the completion of the pnoise simulation. An example of the Direct plot that outlines how to access the cycle-to-cycle jitter results is at URL:

How to get Jee, Jc, and Jcc from transient simulation of driven circuit

This note also provides the relationship between Jcc, period jitter and the absolute jitter Ocean function absjit() and uses the relationship to determine the cycle to cycle jitter as well as how to setup the sampled jitter GUI.

Martin Schmidt said:

The oscillator frequency depends on the time constant of resistor and cap. Main noise sources are flicker noise in the CMOS current mirrors and the CMOS comparator. The oscillator core behaves like a saw-tooth generator, the comparator rectifies the signal.

I am quite familiar with relaxation based VCO having been responsible for designing this VCO topology. In my experience, the comparator delay and its resulting noise played a significant role in both its frequency of oscillation as well as its phase noise. Hence. I was a little surprised to read your comment "...oscillator frequency depends on the time constant of resistor and cap." Perhaps you meant this anyway...

Martin Schmidt said:

All in all I'm not sure if pnoise is well suited for my circuit because of the rectification inside the oscillator. Small noise amplitudes may cause large differences in the output signal. What is your opinion? 

A pss analysis is a large signal based simulation and will definitely include the non-linearity within your VCO (including rectification) - so it does appear to be the proper simulation....once again...my opinion!

Anyway, I appreciate your background information and hope this provides a little more insight or ideas to you in your search for the "right methodology" for your basic issue.

Shawn

Dear Shawn,

I think I got it now. I had a wrong understanding of the output noise spectrum in sampled noise mode.

Here is the oscillator output noise for time average mode (absolute frequency). We can see the noise around the main oscillator frequency and its odd harmonics (rectangular output waveform).

This is the same but with relative frequency:

Here is the result in sampled mode. We can see even harmonics too and a much higher absolute values. I guess, this is the output spectrum after sampling. If this is the case, it does not make sense to integrate over the full spectrum to calculate the time jitter. The results are plausible if I only integrate until half of the clock frequency. I also saw this in two of the Cadence examples, but did not find any note that other upper frequency do not make any sense.

Ok, I'm happy with the results. They match well to transient noise results too. Same for the number of cycles feature in sampled mode. In addition, I got more insights on the top noise contributors.

ShawnLogan said:

Assuming you know the maximum number of successive periods of your oscillator output that form the "longest output pulse on system level", I would include an ideal frequency divider (i.e., noiseless) following your relaxation oscillator.

This is a good hint, I was not thinking in that direction. For now, it seems that the number of cycles feature does the job. But it is always good to have a plan B ;)

ShawnLogan said:

In my experience, the comparator delay and its resulting noise played a significant role in both its frequency of oscillation as well as its phase noise.

Good point, but for this design the comparator delay is less than 5% of the oscillator period.

Thanks again for your support!

Martin

Dear Martin,

Great! Thank you for your kind and interesting update!

Shawn