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Distinguish same cell coming from 2 different sources

This has been a quite non-trivial problem for me.

Let's say I have a NAND2 gate. I have a schematic of it with (In, Out, VDD, VSS) pins. I also have a verilog file of it (outside Cadence) with NAND2(In, Out). So no power supply pins for the verilog version.
I'm running a mixed-signal sim. I have a verilog module that instantiating the verilog NAND2. Also outside this verilog module, I have several analog blocks that using schematic NAND2.
Cadence will get confused and either use only the verilog or the schematic of NAND2 for both analog-block and digital-module. (There will be different kinds of errors)

I have tried to use -y and -v options, and also tried to precompile the digital module into a library using -reflib, but the problem still persists.

What is a good way to overcome this?

Andrew Beckett over 4 years ago

Hopefully you did this already, but contacting customer support would have been the best option here. This is solvable - but rather than putting together an example to illustrate it, it would be much easier (and less error prone) for an application engineer to see precisely what you've got.

Andrew
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