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Obtaining power traces using Cadence Virtuoso

birjit

I am a beginner with the Cadence tools. I have an algorithm, AES-128, written in Verilog. I wish to obtain the current traces of the AES circuit using Cadence Virtuoso. Can someone kindly guide me in this regard?

(The attached figure depicts the whole scenario.)

Parents

  • What do you mean by "current traces"? If you're looking for the current consumption of a digital block, you firstly would need to have an implementation (e.g. using standard cells rather than a behavioural or RTL description of the algorithm), maybe produced using synthesis of the RTL to a particular standard cell library. You could probably use a tool such as Joules RTL to assess the power usage of this block (note that this is not part of the Virtuoso family - if this is what you want, I'll move this to the digital implementation forum). Alternatively you could simulate at transistor level (e.g. using Spectre, maybe Spectre XPS) and measure the actual currents into the supply - but that will of course be significantly slower.

    By the way, you also tried posting the same question to the Logic Design forum (which is moderated) and I didn't allow that post since you'd specifically asked about Virtuoso, and the forum guidelines ask you not to post the same question in more than one forum (as it's a waste of valuable time for those in the community to have to answer it twice).

    Andrew

Reply

  • What do you mean by "current traces"? If you're looking for the current consumption of a digital block, you firstly would need to have an implementation (e.g. using standard cells rather than a behavioural or RTL description of the algorithm), maybe produced using synthesis of the RTL to a particular standard cell library. You could probably use a tool such as Joules RTL to assess the power usage of this block (note that this is not part of the Virtuoso family - if this is what you want, I'll move this to the digital implementation forum). Alternatively you could simulate at transistor level (e.g. using Spectre, maybe Spectre XPS) and measure the actual currents into the supply - but that will of course be significantly slower.

    By the way, you also tried posting the same question to the Logic Design forum (which is moderated) and I didn't allow that post since you'd specifically asked about Virtuoso, and the forum guidelines ask you not to post the same question in more than one forum (as it's a waste of valuable time for those in the community to have to answer it twice).

    Andrew

Children
  • in reply to Andrew Beckett
    By current traces, I am referring to a transient analysis plot of current/power consumed by my AES block during its operation for a particular input. I have already performed the standard-cell level implementation of AES on Virtuoso, however, I don't have the transistor-level schematic implementation of the standard cell gates. But, I have SPICE code of the standard cell gates. 
    Upon reading the documentation of Virtuoso, I got an idea to use "Spectre" to obtain the current/power traces using SPICE file and standard cell Verilog file. Using this idea, I created a .scs file in which I have included the spice file and Verilog file. Also, the .vec file was included to supply inputs.
    The code of .scs file: 
    simulator lang = spectre
    global 0 VDD VSS VBN VBP
    vlog_include "outputs_Feb02-10:50:01/rolling_aes_m.v" supply0 = gnd supply1 = VDC insensitive = no
    pspice_include cad/StdcellLibs/UMC65/G-9LT-LOGIC_MIXED_MODE65N-LL_LOW_K_UMK65LSCLLMVBBR-LIBRARY_TAPE_OUT_KIT-Ver.B03_P.B/UMK65LSCLLMVBBR_B03_TAPEOUTKIT/cir/uk65lscllmvbbr.cir                                                          
    v3 (clk 0) vsource type=pulse va10=0 va11=1.1 delay=0 rise=0 fall=0 width=25n period=50n
    vec_include "input.vec"
    VDC (VDD 0) vsource dc=1.1 type=dc
    v2 (VSS 0) vsource dc=0 type=dc
    v4 (VBN 0) vsource dc=0 type=dc
    v5 (VBP 0) vsource dc=1.1 type=dc
    mytran tran skipstart=0 skipstop=550n strobeperiod=.1n
    save rolling_aes_m.VDC:pwr
    And vec file code that I had created is:
    radix 44444444444444444444444444444444 444444444444444444444444444444444 1 444444444444444444444444444444444
    io iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii i oooooooooooooooooooooooooooooooo
    vname plaintext[[0:127]] key[[0:127]] sel ciphertext[[0:127]]
    tunit ns
    trise 0.0
    tfall 0.0
    vih 1.1
    vil 0.0
    voh 0.9
    vol 0.3
    0 25eb8c48ff89cb854fc09081cc47edfc 00112233445566778899aabbccddeeff 1 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
    30 25eb8c48ff89cb854fc09081cc47edfc 00112233445566778899aabbccddeeff 0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
    When I am runing this file with the command:

    spectre osc.sec
    I am getting these errors:
    Error found by spectre during circuit read-in.
        ERROR (SFE-874): "osc.scs" 5: Unexpected operator "/". Expected end of file or end of line.
    Notice from spectre during Digital Vector read-in.
        Process Vector Files.
    File read: input.vec
    Error found by spectre during Digital Vector read-in.
        ERROR (USIMPRS-17704): The number of names do not match the number of vectors. Change the number of names to match the number of vectors and run the
            simulation again.
            **** Statement details for above warning or error ****
             Statement: vname plaintext[[0:127]] key[[0:127]] sel ciphertext[[0:127]]
             File Name: input.vec
             Line Number: 3
            **** End of Statement details ****
    Is it possible to get the power traces using this idea? If it is possible, how can these errors be resolved?
    [Apologies for posting the same question in multiple forums.]
  • in reply to birjit

    The first issue is that you almost certainly should not be using pspice_include as I rather doubt that it's a PSPICE file. Use include instead.

    The second issue is that the file should be in quotation marks:

    include "cad/StdcellLibs/UMC65/G-9LT-LOGIC_MIXED_MODE65N-LL_LOW_K_UMK65LSCLLMVBBR-LIBRARY_TAPE_OUT_KIT-Ver.B03_P.B/UMK65LSCLLMVBBR_B03_TAPEOUTKIT/cir/uk65lscllmvbbr.cir"

    The vector file has a problem with the radix line. The second and fourth radix has 33 "4" rather than 32, so that means it would be expecting a bus of 132 bits wide not 128 bits wide for key and cipertext. So remove one of each of the extra "4" from the radix line. The io line only really needs to be (I don't think it needs to match the width of the vector):

    io i i i o

    Andrew.

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