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DRC Error - "p substrate stamp error mult" and "p substrate stamp error connect" in gpdk 90

Jayanta

Hi,

I am trying to draw layout of two inverters connected in series. The first inverter body and source are connected but in second inverter, the body of NMOS is not tied to source instead it is connected to a different pin i.e. i am trying to apply body bias to second inverter. While going for DRC check, it showing error like p substrate stamp error mult" and "p substrate stamp error connect". The schematic and layout is attached here. I am using gpdk 90 nm technology in cadence environment. Please help me in solving this problem.

Regards,

Jayanta

  • This is because you have a p-substrate, which is conducting. Consequently the bulks of the NMOS transistors are connected (albeit resistively) and so you can't really apply a different bias to the bulk of NMOS transistors in this technology. PMOS transistors are different - because they sit in an NWell, and so can be isolated.

    I'm not sure what all the layers are in the layout above - it's hard to see. I think that's your problem though.

    Andrew 

  • in reply to Andrew Beckett

    Dear Andrew,

    Thanks for the reply. Is there any means by which we can segregate the NMOS transistors as I have read in one article, a triple well technology will segregate the local and global substrate, but I do not know how to  implement it in this technology. Would you please suggest.

    And as you mentioned PMOS transistors sit in Nwell, so can we apply different body potential to different PMOS in the same design?

    Regards,

    Jayanta

  • in reply to Jayanta

    Neither gpdk090 (nor gpdk045) are triple well technologies and don't have a deep nwell. Of course, the technology is fictional so in principle you could create your own based on the current PDK but that would be a significant amount of work since none of the DRC/LVS rules support it, the technology file doesn't support it, the devices and models don't either.

    Perhaps you should look at a real technology that provides triple well?

    Yes, you can apply different bulk potential to the PMOS devices since they can sit in separate Nwells.

    Andrew

  • in reply to Andrew Beckett

    Thanks a lot for the valuable information, Andrew.

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