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A VerilogA Synchronous Waveform Generator

FAwqati
Hello,
Very excited about my first Mixed-Signal Design Forum post. 
Im looking for some high-level advice of how one would go about implementing what im calling a “Synchronous Waveform Generator”.  I really believe this would be incredibly useful for anyone designing mixed signal circuits.
I would like to be able to instantiate a block (presumably verilogA) in my schematic for spectre only simulations, as im trying to avoid ams co-simulation for a number of reasons. I imagine this block would have 2 input pins (reset and clock) and a digital bus output (something similar to busset as shown below).
It would need to read an input (perhaps a csv / text file) where each line contains a pair of state (digital word specified in binary or hex) and an integer number of clock cycles. With Reset, it starts on the first line and applies the digital word. Then on the positive edge of the clock it will start to iterate through the sequence for the given number of cycles of each state. Very similar to a state machine.
0b1111 , 13
0b1010 , 4
0b1100 , 1

Thank you for you time and effort in advance, 

Faisal

  • Any input would be sincerely appreciated please.

    Also another couple of additions if possible ?

    • Has the ability to loop for periodicity
    • its implemented in VerilogA to avoid hidden states to allow running in PSS

  • in reply to FAwqati

    Hi Faisal,

    Unfortunately I didn't have the bandwidth to spend on this so far, and to be honest, with the requirement to make it hidden-state free, that makes it significantly harder (so I really am not going to find the time to do this any time soon). Maybe somebody else will be able to though...

    Andrew

  • in reply to Andrew Beckett

    Good morning Andrew,

    I certainly can relate/sympathise with respect to bandwidth.

    Regarding this feature, i have decided to change tack. For reference, i think a more straightforward approach is to automate PWL source generation using SKILL.

    I will repost here once i have a working solution.

    Faisal

  • in reply to FAwqati

    Hi Faisal,

    Actually the basic model wouldn't be too hard - making it RF-safe might be more probematic. If it had been just a signal source, it could have been marked as an instrumentation module, but if there are dependencies on the reset and clock inputs, that wouldn't be a safe thing to do. I'm not even sure that it's really possible to have something that reads a file being safe to work in RF analyses, because the file handle itself would be a hidden state (or hide a hidden state). I've not done the checks to be sure - it's possible that this might not work in RF analyses even if it doesn't report the handle as a hidden state variable (this is why I've been non-commital as I know it may need significant time to prove this out).

    Anyway, hopefully you can find a way forward!

    Regards,

    Andrew

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