Define a node as Hi Z in verilog-A

Well, in Verilog-A that would just mean that your modelling of the impedance becomes very high, or you have no current flowing to that pin. It's rather hard to answer this generically without an understanding of what you are actually modelling and what your model looks like.

Andrew.

Hi Andrew,

Thanks for your reply.

I am modeling a tg gate in verilog-A. When enable=0 the output should be at hi'z. How can I model this?

`include "constants.vams"
`include "disciplines.vams"

module rxif_tg_cell(sig_d, sig_s, avdd_hv, avss, d_en_hv);
inout sig_d;
electrical sig_d;
inout sig_s;
electrical sig_s;
input avdd_hv;
electrical avdd_hv;
input avss;
electrical avss;
input d_en_hv;
electrical d_en_hv;

integer d_en_hv1;

parameter real tdelay=1e-12, trise=1e-12, tfall=1e-12;
real out;

analog begin

@(initial_step) begin
d_en_hv1=0;
end

@(cross(V(d_en_hv) - V(avdd_hv)/2, -1)) d_en_hv1=0;
@(cross(V(d_en_hv) - V(avdd_hv)/2, 1)) d_en_hv1=1;

if(d_en_hv1==1) begin
out=V(sig_s);
end

else begin
//here I want to assign the out as hi z
end

V(sig_d) <+ transition(out,tdelay,trise,tfall);

end

Dear bigram94,

bikram94 said:

I am modeling a tg gate in verilog-A. When enable=0 the output should be at hi'z. How can I model this?

If I may echo Andrew's suggestion, is there a reason you can't use a high value resistor to model a high impedance state? As an example of the code for a resistor from the ahdl library, the veriloga for a resistor is attached in the following text file.

This file can be found at your UNIX path of:

<Cadence install directory>/dfII/samples/artist/ahdlLib/res/veriloga/veriloga.va

Shawn

`include "discipline.h"
`include "constants.h"

// $Date: 1997/08/28 05:46:25 $
// $Revision: 1.1 $
//
//
// Based on the OVI Verilog-A Language Reference Manual, version 1.0 1996
//
//
//--------------------
// res
//
// -  resistor
//
// vp,vn:	terminals (V,A)
//
// INSTANCE parameters
//    r = resistance (Ohms)
//
// MODEL parameters
//    {none}
//

module res(vp, vn);
inout vp, vn;
electrical vp, vn;
parameter real r = 0;

   analog
      V(vp, vn) <+ r*I(vp, vn);

endmodule

Dear bikram94 (I apologize for misspelling your name in my prior post!),

It struck me my answer may not be sufficiently clear and thought I should append it with a bit more detail...

When in its high-impedance state, one assigns the output node of your tg to one of the terminals of the veriloga defined resistor whose value is what you consider large (1 Meg, 10 Mheg, 100 Meg...depends on your circuit) and the other terminal to either your supply voltage node, ground, or some fixed bias voltage. Hence, this will appear as a high impedance output node.

When your tg is not its high impedance node, you might still connect one terminal of a different veriloga defined resistor with a much smaller value (1 ohm, 10 ohms,100 ohms ?) to the output and its other terminal to the existing output terminal of your code V(sig_s). This latter suggestion is just an option and you need not include a second resistor.

I hope this allows you to better understand my prior post! Sorry for duplicate post!

Shawn

Hi ShawnLogan,

Thanks for your valuable information. 

I have modeled the tg as you suggested but I am also getting the output when en=0. 

====code====

`include "constants.vams"
`include "disciplines.vams"

module rxif_tg_cell(sig_d, sig_s, avdd_hv, avss, d_en_hv);
inout sig_d;
electrical sig_d;
inout sig_s;
electrical sig_s;
input avdd_hv;
electrical avdd_hv;
input avss;
electrical avss;
input d_en_hv;
electrical d_en_hv;

integer d_en_hv1;

parameter real tdelay=1e-12, trise=1e-12, tfall=1e-12;

analog begin

@(initial_step) begin
d_en_hv1=0;
end

@(cross(V(d_en_hv) - V(avdd_hv)/2, -1)) d_en_hv1=0;
@(cross(V(d_en_hv) - V(avdd_hv)/2, 1)) d_en_hv1=1;

if(d_en_hv1==1) begin
V(sig_s,sig_d) <+ 100*I(sig_s,sig_d);
end
else begin
V(sig_s,sig_d) <+ (1e+12)*I(sig_s,sig_d);
end

end

endmodule

This is presumably because the other side of the transmission gate is open-circuit. If there's no resistive path on that node, then of course it would still follow the input - albeit via a 1TOhm resistance. If (for example) I add a 1MOhm load to ground on the other side of the switch, then you'll see the correct behaviour.

There is another approach, which is to us a switch branch - like this:

if(d_en_hv1==1) begin
  V(sig_s,sig_d) <+ 100*I(sig_s,sig_d);
end
else begin
  I(sig_s,sig_d) <+ 0;
end

This is where the branch changes from a voltage based branch to a current based branch - and as you can see, the else part is open circuit. However, if you use this with nothing connected to the transmission gate output, you will get a convergence failure in the simulator - because the open side of the transmission gate is completely floating, and there is nothing to control it - this means there are an infinite number of solutions and essentially it's an ill-conditioned problem. For normal circuits, there would be some "gmin" type impedance to ground - so you could implement that by doing:

if(d_en_hv1==1) begin
  V(sig_s,sig_d) <+ 100*I(sig_s,sig_d);
end
else begin
  I(sig_s,sig_d) <+ 0;
end
// gmin impedances to prevent floating nodes
I(sig_s,avss) <+ V(sig_s,avss)*1e-12;
I(sig_d,avss) <+ V(sig_d,avss)*1e-12;

Then you can leave the output of the transmission gate open-circuit (which is probably unrealistic usage anyway). It avoids you having to add a high impedance load to the output, but that's probably sensible anyway - it's very unlikely that there is absolutely no leakage path from the output to ground.

Regards,

Andrew.

Dear Andrew,

Thank you for answering bikram94's question concerning the output still following the input! Your response is indeed absolutely correct! As Andrew noted, if you include some reasonable real impedance (1K, 10K?) at the output to, for example, ground, then the amount of the coupling to the output will be reduced as the resistance divider ratio will be reduced relative to your existing circuit with an infinite impedance at the output.

Does this make some sense bikram94?

Shawn