For my design, it would be very useful to declare an array with two dimensions.
However, I have still syntax errors when I try this construction.
It is true that in the LR 20.1 there is nothing about this kind of construct.
On the other hand, Accelera LRM postulated this construct already in 2014.
Is it still not implemented in Cadence Verilog-A or Verilog-AMS?
Is it any other solution to this issue at Cadence?