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I want to include few veriloga models which i am instantiating inside my parent block. I am including it as follows at the beginning of parent block :
When i am doing a extract i get a error saying port mismatch between module and symbol.
Is this a correct approach. if not kindly guide me.
You wouldn't normally include the code for a sub-module this way. You'd normally just instantiate the blocks (using structural Verilog-A statements) and then the netlister would take care of including the Verilog-A code of the sub-blocks.
I have few veriloga codes ( Level shifters mainly ) that i want to instantiate ( not present in Library Manager) inside my Parent block in order to get correct functionality of the block.
I have made those cells separately and have instantiated same in my veriloga code. It's a hierarchically coded block where i am calling other instances too. Is there a better way to deal with it ? `include does not seem to work
Why not just make separate cells from them in Virtuoso (so they will show up in the library manager)? In general Virtuoso is much happier if you have a single module per view, and this fits far better with use of the hierarchy editor to do view-switching. It also prevents strange problems caused by including the same module in multiple modules and ending up with clashes and duplicates.
The above graphic might help understand the issue better.
As suggested, I removed all the `includes. It does get netlist now.
When i am netlisting the above, in netlist.vams i am only getting the Instantiation of the above parent block with its port mapping. All the module definitions of the sub blocks which are instantiated inside are missing. What am i missing ?
All these models are present as corresponding cell views in a seperate master library. I dont have the permission to create a new cell to the above library so i can only create the view in a different library.
The LS ( Level shifter ) block does not exist in the design as a seperate symbol or entity, it exists as a MOS circuit one level down to where i have modelled. This is the major reason why i am modelling the block one level up to remove the MOS from the picture. In the process i am facing the above issues.
How to achieve the above ?
Pardon if i am missing something.