PSS failure for a ring VCO

Dear Subhadeep,

Thank you for the detailed description of your design and methodology - I found your description quite useful!

subhadeepdatta said:

Can you tell me what is causing PSS not to converge in this case?

I canot be sure, of course, but I did notice one item that I might suggest you re-consider...let me know your thoughts...

subhadeepdatta said:

• forcing complementary signals (ring-top voltage and VSS) to one of the ring output pairs from the test-bench level using ideal switches and analogLib pwl source.
• using "initial conditions" from ADEXL test to set complementary signals to one of the ring output pairs.

Actually, if you consider what your two bullet items are doing, they are actually setting the gain of the VCO to zero. -which is exactly what you do not want to do to ensure a robust start-up process! Why do I note this? The fact that a differential pseudo-CMOS 4 stage ring oscillates is a result of one or more of the differential inverter stages being in or near its high gain region. When the output of one differential stage assumes a complementary logic state of "1" or "0", this merely limits the amplitude of the oscillations as it represents a very low gain and saturated state. In the course of a steady-state oscillation, some stages are close or near their high gain regions and others may be close to a complementary logic state. Therefore, to assure a robust start-up process, the most appropriate initial condition for the inverter stages is one where each stage is in its high gain region - where its outputs are far from their saturated states of a logic one or zero. In this fashion, any small amount of circuit or numerical noise will be amplified by each stage successively to build up to a steady-state oscillation determined by the propagation delay time of your inverter stages.

It is rather common to find that, without forcing this high gain state at circuit power-up or the start of a transient simulation, a ring VCO may not start properly and result in no oscillations under some conditions. I believe this is why you happened to observe steady-state oscillation in your conventional transient simulation, but not in the tstab portion of the pss transient simulation. In many rings that I have designed, I purposefully add circuitry to enforce the high-gain region to exist in the inverter stages as actual ring VCO used in products must show a highly reliable start-up process. If this is not something you want to include Subhadeep, perhaps you can add initial conditions to set the input and output voltage nodes of your inverters to a value close to 50% of your supply voltage. In this fashion, the DC solution at the beginning of the tstab portion of the pss simulation will result in a relatively high gain for each stage of the ring. Hopefully, as the DC solution is released and the integration starts, the noise will be amplified sufficient;y to produce a steady-state oscillation. To verify the initial conditions are setting the gain sufficiently high as the simulation starts, you can run a set of AC tran simulations at several time points of a transient simulation and study the small-signal gain of your VCO versus time to assure that the gain is sufficiently high as the simulation starts.

Let me know your thoughts Subhadeep. If my comments are not sufficiently clear to you, please let me know and I will try again!

Shawn

Shawn

Thanks Shawn for such an elaborate reply. I do agree with you that initializing the ring-VCO nets to mid-rail is going to be the best strategy for a robust start-up because this ensures that all of the inverters are in high-gain region and a small enough numerical noise in simulation or circuit noise in silicon will reliably start the VCO oscillation. You mentioned something related to having a certain circuitry to ensure this part, can you brief me more on that? What kind of circuit(s) do you use to do that? I have seen one start-up circuit technique where a differential kick is given to the other side of the ac-coupling cap of the VCO buffer which then couples it to the ring and starts it up.

As far as the simulation is concerned, initializing ring nets to the mid-rail also did not help. Still having the same issue. Output log shows that the PSS runs for some time and then it says that the voltage of the ring output is too small to reliably detect the period of the oscillator. Perhaps the nodes with insignificant signal levels were chosen, or perhaps the oscillator was never properly started.

Do you have any other suggestions? 

I would say it's a fairly unusual way of getting a ring oscillator to start to initialise to mid-rail and hoping that numerical noise will start it. The normal DC algorithm is likely to do that anyway - because it could end up being a metastable state where everything sits at mid-rail. Unless something changes, there's no reason why a time-domain simulation would move away from that metastable state unless there's enough time steps and numerical noise to move away from that point. It will probably startup, but it would be slower to get there and need more time steps to encourage it to do so.

The point of holding (with an initial condition) a node in the ring either high or low is that that inconsistency in the ring is not going to be sustainable - you've held it high, but having been through an odd number of inverters to get back to that point, it ought to be low  - and so when the initial condition is removed, it will immediately have to try to fix the inconsistency and that will normally cause the inversions to propagate through the ring oscillator.

Anyway, I've not had time to reflect on anything else in this discussion as I'm going to be on vacation for 10 days or so, so I can't spend more time responding, sorry!

Andrew

Dear Subhadeep,

Thank you for your added information. I will comment on the two items you mentioned if you have the time and patience!

subhadeepdatta said:

You mentioned something related to having a certain circuitry to ensure this part, can you brief me more on that? What kind of circuit(s) do you use to do that?

Yes. However, I am concerned about describing the circuit as it is a company proprietary design. Hence, unfortunately, I don't think it is appropriate for me to provide a description with sufficient information to duplicate it in your application...please try to understand my quandry!

However, I will indicate that it is not similar to the description of the start-up circuit technique you provided in your post.

subhadeepdatta said:

As far as the simulation is concerned, initializing ring nets to the mid-rail also did not help. Still having the same issue. Output log shows that the PSS runs for some time and then it says that the voltage of the ring output is too small to reliably detect the period of the oscillator.

1. Did you examine the small-signal gain using a series of AC times simulations in a conventional transient analysis to validate the circuit was in its high gain region?

2. Did you use nodesets or initial conditions to "initialize ring nets to the mid-rail"? A nodeset willl not hold the DC value you specify at the start of the simulation, but only serve as a "guide" for the DC solution.

3. Have you saved and subsequently observed the tstab portion of the pss simulation? This will clearly show the waveforms prior to the pss simulation where it attempts to arrive at its estimate of the steady-state solution. If so, might you describe the waveforms?

4. Another common technique to start a ring is to ramp the supply voltage from ground to its nominal value. This can also be done in the tstab portion of a pss simulation using a piecewise linear supply for the supply voltage (perhaps with an added series RC time constant to avoid the discontinuity as the slope instantaneously changes from 0 to the rise time region of the piecewise linear source). It is not as reliable a start-up method as the method I proposed, but may be an alternative to explore. Is this something you have already tried?

5. One other thought, which I know Andrew has advised on many occasions is not one he recommends but which in my experience has been helpful, is to make sure your maximum integration timesteps are much less than the 5 GHz ring oscillator period of 200 ps. For example, if you are running spectre or spectre +aps, you can add the parameter maxstep= 200 ps/20 to enforce that the simulator take at least 20 steps over the 200 ps  period. This basically sets the maximum integration time step to10 ps. Perhaps a 20 ps maxstep might be a reasonable value to start with. If you are running spectre X, you will need to override its behavior to add the "maxstep" criteria.

Just a few thoughts that I hope will help or provide some insight on your observations to date Subhadeep as you attempt to complete a pss analysis....these issues are rather common in oscillator design. Although oscillators appear to be very simple circuits, they have been studied theoretically since the 1920's and remain a source of much discussion (and sometimes grief!!). Hang in there and don't give up!

Shawn