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Different results using AMS simulator vs. Spectre simulator

Hello,

When simulating a very basic ring oscillator using some standard library inverter, the resulting output frequency is different when using spectre as the selected simulator compared to selecting AMS as a simulator.
I know that there is no need to use the AMS simulator when only analogue circuits are simulated.
However, because in the future I will need to run mixed mode simulations, I was verifying if I got the same output results across both simulators.

The testbench contains an inverter ring of 51 cells. When running a spectre simulation the output frequency is 846 MHz, when running the same testbench with the AMS simulator the output frequency is 966MHz.
To my opinion, this is quite a large difference. Does anybody know a possible cause for this difference in results? Maybe a setting that I'm missing?

Thanks In advance.

Bjorn

Parents

ShawnLogan over 4 years ago

Dear Bjorn,

To be honest, it is not clear to me how valid your comparison between the ring VCO frequency is between the two simulators. Among the items that come to mind that are not evident from your question are:

1. Versions of each simulator

2. What type of simulation you are performing in each simulator.

3. Specific simulator options chosen for each simulation for the two simulators

4. Netlists for each simulator and their output logs

5. Power supply voltages applied to each simulator (and control voltages perhaps)

Speaking for myself, I don't think I can provide any thoughts without knowing more about each of these items. Perhaps others with more expertise than I who read this forum can without this added information.

Shawn
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Bjorn VB over 4 years ago in reply to ShawnLogan

Dear Shawn,

Here is some more detail about the simulations and the tools i'm using.

cadence Virtuoso: version IC6.1.8-64b.500.10

spectre: version 20.1.0.099.isr2 64bit -- 3 Dec 2020

xrun: version 20.03-s007

the simulation is a transient simulation of 40ns with transient noise enabled.
The testbench uses a config file, which is required to perform an AMS simulation.
The circuit is verified in ADE Assembler. It is in ADE that I change the simulator from spectre to AMS, and keep al other settings the same.

For the regular spectre simulation, the redacted logfile is linked below.

Fullscreen Spectre_Log.txt Download

Spectre (R) Circuit Simulator
Version 20.1.0.099.isr2 64bit -- 3 Dec 2020
Copyright (C) 1989-2020 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: ***   Host: ***   HostID: ***   PID: ***
Memory  available: 30.2014 GB  physical: 135.4741 GB
Linux   : Red Hat Enterprise Linux Server release 6.10 (Santiago)
CPU Type: Intel(R) Xeon(R) CPU
All processors running at 2800.2 MHz
        Socket: Processors (Hyperthreaded Processor)
        0:       0 ( 12 ),  1 ( 13 ),  2 ( 14 ),  3 ( 15 ),  4 ( 16 )
                 5 ( 17 ),  6 ( 18 ),  7 ( 19 ),  8 ( 20 ),  9 ( 21 )
                10 ( 22 ), 11 ( 23 )
        
System load averages (1min, 5min, 15min) : 3.5 %, 3.8 %, 2.5 %
Hyperthreading is enabled
HPC is enabled

Simulating `input.scs' on *** at 8:57:11 AM, Tue Aug 31, 2021 (process id: 28043).
Current working directory: /***/project/***/simulation/***/ringosc/maestro/results/maestro/Interactive.18/1/***:ringosc:1/netlist
Command line:
     \
        /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/bin/spectre  \
        -64 input.scs +escchars +log ../psf/spectre.out -format psfxl  \
        -raw ../psf ++aps +mt=4 +lqtimeout 0 -maxw 5 -maxn 5 +lqsleep  \
        30 +lsusp -env ade -ahdllibdir  \
        /***/project/***/simulation/***/ringosc/maestro/results/maestro/Interactive.18/sharedData/CDS/ahdl/input.ahdlSimDB  \
        +logstatus

Loading /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...
Loading /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ...
Loading /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...
Loading /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...
Loading /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...
Reading file:  /***/project/***/simulation/***/ringosc/maestro/results/maestro/Interactive.18/1/***:ringosc:1/netlist/input.scs
Reading file:  /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /***/pdks/***/***/models/***/***.scs
Reading file:  /***/pdks/***/***/models/***/***.scs
Time for NDB Parsing: CPU = 1.20082 s, elapsed = 1.28792 s.
Time accumulated: CPU = 1.26981 s, elapsed = 1.28793 s.
Peak resident memory used = 101 Mbytes.

Time for Elaboration: CPU = 30.996 ms, elapsed = 32.0132 ms.
Time accumulated: CPU = 1.3008 s, elapsed = 1.32007 s.
Peak resident memory used = 111 Mbytes.

Warning from spectre during hierarchy flattening.
    WARNING (SPECTRE-17101): The value 'psf' specified for the 'checklimitdest' option will no longer be supported in future releases. Use 'spectre -h' to see other recommended values for the 'checklimitdest' option.

Time for EDB Visiting: CPU = 2.999 ms, elapsed = 2.86984 ms.
Time accumulated: CPU = 1.3038 s, elapsed = 1.32305 s.
Peak resident memory used = 112 Mbytes.

Notice from spectre during initial setup.
    Multithreading is disabled due to the size of the design being too small.

Global user options:
         psfversion = 1.4.0
            vabstol = 1e-06
            iabstol = 1e-12
               temp = 27
               gmin = 1e-12
             rforce = 1
           maxnotes = 5
           maxwarns = 5
             digits = 5
               cols = 80
             pivrel = 0.001
           sensfile = ../psf/sens.output
     checklimitdest = psf
               save = allpub
             reltol = 0.0001
               tnom = 27
             scalem = 1
              scale = 1

Scoped user options:

Circuit inventory:
              nodes 54
              bsim4 408   
            vsource 3     

Analysis and control statement inventory:
               info 7     
               tran 1     

Output statements:
             .probe 0     
           .measure 0     
               save 0     

Notice from spectre during initial setup.
    2 vsources are short because their absolute value is less than or equal to 'vabsshort'.
    Fast APS Enabled.

Time for parsing: CPU = 4.999 ms, elapsed = 20.6871 ms.
Time accumulated: CPU = 1.3088 s, elapsed = 1.34385 s.
Peak resident memory used = 113 Mbytes.

~~~~~~~~~~~~~~~~~~~~~~
Pre-Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~

Notice from spectre during transient analysis `tran'.
    Specified 'noisefmin' is smaller than 1/stop time. 'noisefmin' has been changed to 25 MHz.

************************************************
Transient Analysis `tran': time = (0 s -> 40 ns)
************************************************

Notice from spectre during IC analysis, during transient analysis `tran'.
    There are 1 IC nodes defined.
Notice from spectre during IC analysis, during transient analysis `tran'.
    Bad pivoting is found during DC analysis. Option dc_pivot_check=yes is recommended for possible improvement of convergence.
    Initial condition computed for node ring<51> is in error by 885.175 uV (73.7645 m%).
        Decrease `rforce' to reduce error in computed initial conditions.  However, setting rforce too small may result in convergence difficulties or in the matrix becoming singular.

DC simulation time: CPU = 8.998 ms, elapsed = 9.68313 ms.

Warning from spectre during transient analysis `tran'.
    WARNING: The cm value is specified for the tran analysis fastcross option but this value is supported only by AMS-Ultra or AMS-Spectre integrated with new Front-End. The simulator uses the fastcross discrete value instead of the cm value.

Opening the PSFXL file ../psf/tran.tran.tran ...
Important parameter values:
    start = 0 s
    outputstart = 0 s
    stop = 40 ns
    step = 40 ps
    maxstep = 200 fs
    ic = all
    useprevic = no
    skipdc = no
    reltol = 100e-06
    abstol(V) = 1 uV
    abstol(I) = 1 pA
    temp = 27 C
    tnom = 27 C
    tempeffects = all
    errpreset = moderate
    method = gear2only
    lteratio = 3.5
    relref = sigglobal
    cmin = 0 F
    gmin = 1 pS
    rabsshort = 1 mOhm
    trannoisemethod = default
    noisefmax = 10 GHz
    noisefmin = 25 MHz
    noiseseed = 1

Notice from spectre during transient analysis `tran'.
    Multithreading is disabled due to the size of the design being too small.

Output and IC/nodeset summary:
                 save   1       (current)
                 save   53      (voltage)
                 ic     1       

    tran: time = 1 ns         (2.5 %), step = 143.9 fs     (360 u%)
    tran: time = 3 ns         (7.5 %), step = 200 fs       (500 u%)
    tran: time = 5 ns        (12.5 %), step = 200 fs       (500 u%)
    tran: time = 7 ns        (17.5 %), step = 200 fs       (500 u%)
    tran: time = 9 ns        (22.5 %), step = 200 fs       (500 u%)
    tran: time = 11 ns       (27.5 %), step = 200 fs       (500 u%)
    tran: time = 13 ns       (32.5 %), step = 200 fs       (500 u%)
    tran: time = 15 ns       (37.5 %), step = 200 fs       (500 u%)
    tran: time = 17 ns       (42.5 %), step = 200 fs       (500 u%)
    tran: time = 19 ns       (47.5 %), step = 125 fs       (312 u%)
    tran: time = 21 ns       (52.5 %), step = 200 fs       (500 u%)
    tran: time = 23 ns       (57.5 %), step = 125 fs       (312 u%)
    tran: time = 25 ns       (62.5 %), step = 200 fs       (500 u%)
    tran: time = 27 ns       (67.5 %), step = 200 fs       (500 u%)
    tran: time = 29 ns       (72.5 %), step = 200 fs       (500 u%)
    tran: time = 31 ns       (77.5 %), step = 200 fs       (500 u%)
    tran: time = 33 ns       (82.5 %), step = 200 fs       (500 u%)
    tran: time = 35 ns       (87.5 %), step = 200 fs       (500 u%)
    tran: time = 37 ns       (92.5 %), step = 200 fs       (500 u%)
    tran: time = 39 ns       (97.5 %), step = 200 fs       (500 u%)
Number of accepted tran steps =             200431

Maximum value achieved for any signal of each quantity: 
V: V(I1<48>.MU1_0-M_u3_turbo_m4:int_g) = 1.278 V
I: I(V0:p) = 2.612 mA
If your circuit contains signals of the same quantity that are vastly different in size (such as high voltage circuitry combined with low voltage control circuitry), you should consider specifying global option `bin_relref=yes'.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Post-Transient Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   -   Non-default settings that could significantly slow down simulation
          maxstep = 200 fs, default 800 ps
          reltol = 100e-06, default 1e-03
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


During simulation, the CPU load for active processors is :
         0 (13.8 %)      1 (7.5 %)       2 (19.2 %)      3 (3.1 %)
         4 (2.0 %)       5 (3.2 %)       6 (1.0 %)       7 (1.5 %)
         8 (60.2 %)      9 (1.0 %)      11 (1.9 %)      12 (9.3 %)
        13 (6.0 %)      14 (28.9 %)     15 (1.4 %)      16 (5.4 %)
        19 (1.0 %)      20 (5.3 %)      23 (2.1 %)      
        Total: 177.3%
Initial condition solution time: CPU = 8.998 ms, elapsed = 9.74083 ms.
Intrinsic tran analysis time:    CPU = 23.5784 s, elapsed = 23.5927 s.
Total time required for tran analysis `tran': CPU = 23.5904 s, elapsed = 23.6057 s.
Time accumulated: CPU = 25.3102 s, elapsed = 25.6127 s.
Peak resident memory used = 335 Mbytes.

finalTimeOP: writing operating point information to rawfile.

Opening the PSF file ../psf/finalTimeOP.info ...
modelParameter: writing model parameter values to rawfile.

Opening the PSF file ../psf/modelParameter.info ...
element: writing instance parameter values to rawfile.

Opening the PSF file ../psf/element.info ...
outputParameter: writing output parameter values to rawfile.

Opening the PSF file ../psf/outputParameter.info ...
designParamVals: writing netlist parameters to rawfile.

Opening the PSFASCII file ../psf/designParamVals.info ...
primitives: writing primitives to rawfile.

Opening the PSFASCII file ../psf/primitives.info.primitives ...
subckts: writing subcircuits to rawfile.

Opening the PSFASCII file ../psf/subckts.info.subckts ...

Aggregate audit (8:57:37 AM, Tue Aug 31, 2021):
Time used: CPU = 25.4 s, elapsed = 25.8 s, util. = 98.6%.
Time spent in licensing: elapsed = 10.7 ms.
Peak memory used = 336 Mbytes.
Simulation started at: 8:57:11 AM, Tue Aug 31, 2021, ended at: 8:57:37 AM, Tue Aug 31, 2021, with elapsed time (wall clock): 25.8 s.
spectre completes with 0 errors, 2 warnings, and 9 notices.

For the AMS simulation, the redacted logfile is linked below.

Fullscreen AMS_Log.txt Download

xrun(64): 20.03-s007: (c) Copyright 1995-2020 Cadence Design Systems, Inc.
TOOL:	xrun(64)	20.03-s007: Started on Aug 31, 2021 at 09:01:43 CEST
xrun
	-f xrunArgs
		-UNBUFFERED
		-cdslib ./cds.lib
		-errormax 50
		-status
		-nowarn DLNOHV
		-nowarn DLCLAP
		-v93
		-incdir /***/project/***/***/
		-ade
		-timescale 1fs/1fs
		-vtimescale 1fs/1fs
		-delay_mode None
		-novitalaccl
		-access r
		-noparamerr
		-amspartinfo ../psf/partition.info
		-rnm_partinfo
		-modelincdir /***/project/***/***/
		./spiceModels.scs
		./amsControlSpectre.scs
		-input ./probe.tcl
		-run
		-exit
		-xmsimargs "+amsrawdir ../psf"
		-spectre_args "-ahdllibdir /***/project/***/simulation/***/ringosc/maestro/results/maestro/Interactive.19/sharedData/CDS/ahdl/input.ahdlSimDB"
		-simcompatible_ams spectre
		-name ***.ringosc:config
		-allowredefinition
		-amsbind
		-top ***.ringosc:schematic
		-top cds_globals
		./netlist.vams
		./ie_card.scs
		-f ./textInputs
			-makelib tcbn65lp
			-makelib ***
			-endlib
		./cds_globals.vams
		-l ../psf/xrun.log
		-spectre_args ++aps
		-spectre_args +mt=4
file: ./netlist.vams
	module ***.ringosc:schematic
		errors: 0, warnings: 0
	module ***.INV**:schematic
		errors: 0, warnings: 0
file: ./cds_globals.vams
	module worklib.cds_globals:vams
		errors: 0, warnings: 0
xmvlog: *W,SPDUSD: Include directory /***/project/***/***/ given but not used.
	Total errors/warnings found outside modules and primitives:
		errors: 0, warnings: 1
xmvlog: Memory Usage - Current physical: 19.5M, Current virtual: 61.6M
xmvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.1s, 29.5% cpu)
		Caching library '***' ....... Done
		Caching library 'worklib' ....... Done
		Caching library 'tcbn65lp' ....... Done
	Elaborating the design hierarchy:
	Top level design units:
		ringosc
		cds_globals
	Discipline resolution Pass...
	Building instance overlay tables: .................... Done
	Building instance specific data structures.
	Loading native compiled code:     .................... Done
	Design hierarchy summary:
		                 Instances  Unique
		Modules:                53       3
		Interconnect:           55       -
		Simulation timescale:  1fs
	Writing initial simulation snapshot: ***.ringosc:config
xmelab: Memory Usage - Final: 41.7M, Peak: 165.7M, Peak virtual: 274.5M
xmelab: CPU Usage - 0.1s system + 0.1s user = 0.1s total (0.2s, 68.4% cpu)
Loading snapshot ***.ringosc:config .................... Done
	Starting analog simulation engine...
AMSD Flexible Release Matrix --- using Spectre from installation:
    /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/bin/spectre
AMSD: Using spectre solver with arguments: -ahdllibdir /***/project/***/simulation/***/ringosc/maestro/results/maestro/Interactive.19/sharedData/CDS/ahdl/input.ahdlSimDB ++aps +mt=4.
xcelium> source /***/software/Cadence/2015-2016/lnx86/XCELIUM_20.03.007/tools/xcelium/files/xmsimrc
xcelium> 
xcelium> # This is the NC-SIM(R) probe command file
xcelium> # used in the AMS-ADE integration.
xcelium> 
xcelium> 
xcelium> #
xcelium> # Database settings
xcelium> #
xcelium> if { [info exists ::env(AMS_RESULTS_DIR) ] } { set AMS_RESULTS_DIR $env(AMS_RESULTS_DIR)} else {set AMS_RESULTS_DIR "../psf"}
../psf
xcelium> database -open ams_database -into ${AMS_RESULTS_DIR} -default
Created default SHM database ams_database
xcelium> 
xcelium> #
xcelium> # Probe settings
xcelium> #
xcelium> probe -create -emptyok -database ams_database {ringosc.ring[50]}
Created probe 1   #... up to 52

xcelium> run

Spectre (R) Circuit Simulator
Version 20.1.0.099.isr2 64bit -- 3 Dec 2020
Copyright (C) 1989-2020 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: ***   Host: saturn.c.fusion-2016.internal   HostID: 840A1900   PID: 30885
Memory  available: 30.1003 GB  physical: 135.4741 GB
Linux   : Red Hat Enterprise Linux Server release 6.10 (Santiago)
CPU Type: Intel(R) Xeon(R) CPU
All processors running at 2800.2 MHz
        Socket: Processors (Hyperthreaded Processor)
        0:       0 ( 12 ),  1 ( 13 ),  2 ( 14 ),  3 ( 15 ),  4 ( 16 )
                 5 ( 17 ),  6 ( 18 ),  7 ( 19 ),  8 ( 20 ),  9 ( 21 )
                10 ( 22 ), 11 ( 23 )
        
System load averages (1min, 5min, 15min) : 1.0 %, 2.2 %, 2.1 %
Hyperthreading is enabled
HPC is enabled

Simulating `spiceModels.ams' on saturn.c.fusion-2016.internal at 9:01:59 AM, Tue Aug 31, 2021 (process id: 30885).
Current working directory: /***/project/***/simulation/***/ringosc/maestro/results/maestro/Interactive.19/1/***:ringosc:1/netlist
Command line:
     \
        /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/bin/spectre  \
        -64 spiceModels.ams +config  \
        /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/spectre/etc/configs/ams.cfg  \
        -ahdllibdir  \
        /***/project/***/simulation/***/ringosc/maestro/results/maestro/Interactive.19/sharedData/CDS/ahdl/input.ahdlSimDB  \
        ++aps +mt=4 -raw ../psf -I/***/project/***/***/  \
        +ams_control=xcelium.d/AMSD/ams_ctrl/ams_ctrl_29865_saturn.c.fusion-2016.internal
Loading /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...
Loading /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ...
Loading /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...
Loading /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...
Loading /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...
Reading file:  /***/project/***/simulation/***/ringosc/maestro/results/maestro/Interactive.19/1/***:ringosc:1/netlist/spiceModels.ams

Notice from spectre during circuit read-in.
    Configuration file used: `/***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/spectre/etc/configs/ams.cfg'.

Reading file:  /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /***/project/***/simulation/***/ringosc/maestro/results/maestro/Interactive.19/1/***:ringosc:1/netlist/spiceModels.scs
Reading file:  /***/pdks/***/***/models/spectre/toplevel.scs
Reading file:  /***/pdks/***/***/models/spectre/***.scs
Reading file:  /***/project/***/simulation/***/ringosc/maestro/results/maestro/Interactive.19/1/***:ringosc:1/netlist/amsControlSpectre.scs
Reading file:  /***/project/***/simulation/***/ringosc/maestro/results/maestro/Interactive.19/1/***:ringosc:1/netlist/ie_card.scs
Reading file:  /***/project/***/simulation/***/ringosc/maestro/results/maestro/Interactive.19/1/***:ringosc:1/netlist/.amsbind.scs
Reading file:  /***/software/Cadence/2015-2016/lnx86/SPECTRE_20.10.099/tools.lnx86/spectre/etc/configs/ams.cfg
Time for NDB Parsing: CPU = 1.19182 s, elapsed = 1.26543 s.
Time accumulated: CPU = 1.25781 s, elapsed = 1.26543 s.
Peak resident memory used = 106 Mbytes.

Time for Elaboration: CPU = 31.995 ms, elapsed = 33.041 ms.
Time accumulated: CPU = 1.2898 s, elapsed = 1.29858 s.
Peak resident memory used = 115 Mbytes.


Warning from spectre during hierarchy flattening.
    WARNING (SPECTRE-17101): The value 'psf' specified for the 'checklimitdest' option will no longer be supported in future releases. Use 'spectre -h' to see other recommended values for the 'checklimitdest' option.

Time for EDB Visiting: CPU = 2.999 ms, elapsed = 3.09014 ms.
Time accumulated: CPU = 1.2928 s, elapsed = 1.30179 s.
Peak resident memory used = 116 Mbytes.

Notice from spectre during initial setup.
    Multithreading is disabled due to the size of the design being too small.

Global user options:
               temp = 27
            vabstol = 1e-06
            iabstol = 1e-12
               gmin = 1e-12
             rforce = 1
           maxnotes = 5
           maxwarns = 5
             digits = 5
             pivrel = 0.001
     checklimitdest = psf
             rawfmt = sst2
               save = selected
               tnom = 27
              scale = 1
             scalem = 1
             reltol = 0.0001

Scoped user options:

Circuit inventory:
              nodes 56
              bsim4 408   
            vsource 3     

Analysis and control statement inventory:
               info 4     
               tran 1     

Output statements:
             .probe 0     
           .measure 0     
               save 52    

Notice from spectre during initial setup.
    1 vsources are short because their absolute value is less than or equal to 'vabsshort'.
    Fast APS Enabled.

Time for parsing: CPU = 5 ms, elapsed = 16.978 ms.
Time accumulated: CPU = 1.2978 s, elapsed = 1.31888 s.
Peak resident memory used = 118 Mbytes.

~~~~~~~~~~~~~~~~~~~~~~
Pre-Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~

Notice from spectre during transient analysis `tran'.
    Specified 'noisefmin' is smaller than 1/stop time. 'noisefmin' has been changed to 25 MHz.

************************************************
Transient Analysis `tran': time = (0 s -> 40 ns)
************************************************

Notice from spectre during IC analysis, during transient analysis `tran'.
    There are 1 IC nodes defined.
Notice from spectre during IC analysis, during transient analysis `tran'.
    Bad pivoting is found during DC analysis. Option dc_pivot_check=yes is recommended for possible improvement of convergence.
    Initial condition computed for node ringosc.ring[51] is in error by 885.175 uV (73.7645 m%).
        Decrease `rforce' to reduce error in computed initial conditions.  However, setting rforce too small may result in convergence difficulties or in the matrix becoming singular.

DC simulation time: CPU = 10.998 ms, elapsed = 11.8449 ms.

Opening the AMSSST2 file ../psf/psf.trn ...
Important parameter values:
    start = 0 s
    outputstart = 0 s
    stop = 40 ns
    step = 40 ps
    maxstep = 200 fs
    ic = all
    useprevic = no
    skipdc = no
    reltol = 100e-06
    abstol(V) = 1 uV
    abstol(I) = 1 pA
    temp = 27 C
    tnom = 27 C
    tempeffects = all
    errpreset = moderate
    method = gear2only
    lteratio = 3.5
    relref = sigglobal
    cmin = 0 F
    gmin = 1 pS
    rabsshort = 1 mOhm
    trannoisemethod = default
    noisefmax = 10 GHz
    noisefmin = 25 MHz
    noiseseed = 1

Notice from spectre during transient analysis `tran'.
    Multithreading is disabled due to the size of the design being too small.

Output and IC/nodeset summary:
                 save   52      (voltage)
                 ic     1       

    tran: time = 1 ns         (2.5 %), step = 138.7 fs     (347 u%)
    tran: time = 3 ns         (7.5 %), step = 125 fs       (312 u%)
    tran: time = 5 ns        (12.5 %), step = 200 fs       (500 u%)
    tran: time = 7 ns        (17.5 %), step = 200 fs       (500 u%)
    tran: time = 9 ns        (22.5 %), step = 200 fs       (500 u%)
    tran: time = 11 ns       (27.5 %), step = 200 fs       (500 u%)
    tran: time = 13 ns       (32.5 %), step = 200 fs       (500 u%)
    tran: time = 15 ns       (37.5 %), step = 200 fs       (500 u%)
    tran: time = 17 ns       (42.5 %), step = 125 fs       (312 u%)
    tran: time = 19 ns       (47.5 %), step = 125 fs       (312 u%)
    tran: time = 21 ns       (52.5 %), step = 200 fs       (500 u%)
    tran: time = 23 ns       (57.5 %), step = 200 fs       (500 u%)
    tran: time = 25 ns       (62.5 %), step = 200 fs       (500 u%)
    tran: time = 27 ns       (67.5 %), step = 200 fs       (500 u%)
    tran: time = 29 ns       (72.5 %), step = 125 fs       (312 u%)
    tran: time = 31 ns       (77.5 %), step = 200 fs       (500 u%)
    tran: time = 33 ns       (82.5 %), step = 200 fs       (500 u%)
    tran: time = 35 ns       (87.5 %), step = 200 fs       (500 u%)
    tran: time = 37 ns       (92.5 %), step = 200 fs       (500 u%)
    tran: time = 39 ns       (97.5 %), step = 200 fs       (500 u%)

The analog simulator has reached stop time, please use `analog -stop <new stop time>' to extend the analog stop time.
Simulation stopped via transient analysis stoptime at time 39999999 FS
Memory Usage - Current physical: 53.8M, Current virtual: 300.5M
CPU Usage - 14.5s system + 9.4s user = 23.9s total (77.9% cpu)
xcelium> exit
`AutoStop = yes'. Analysis finished at 40 ns.

Number of accepted tran steps =             200872

Maximum value achieved for any signal of each quantity: 
V: V(ringosc.ring[49]) = 1.275 V
I: I(ringosc.V2:p) = 885.2 uA
If your circuit contains signals of the same quantity that are vastly different in size (such as high voltage circuitry combined with low voltage control circuitry), you should consider specifying global option `bin_relref=yes'.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Post-Transient Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   -   Non-default settings that could significantly slow down simulation
          maxstep = 200 fs, default 800 ps
          reltol = 100e-06, default 1e-03
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

During simulation, the CPU load for active processors is :
         0 (82.3 %)      1 (70.6 %)      2 (24.9 %)      3 (8.8 %)
         4 (3.2 %)       5 (8.5 %)       6 (10.4 %)      7 (3.2 %)
         8 (8.1 %)      10 (1.5 %)      12 (5.1 %)      13 (6.8 %)
        14 (8.8 %)      15 (5.0 %)      16 (1.6 %)      17 (1.2 %)
        18 (2.9 %)      19 (12.4 %)     
        Total: 269.6%
Initial condition solution time: CPU = 10.998 ms, elapsed = 11.8971 ms.
Intrinsic tran analysis time:    CPU = 32.1261 s, elapsed = 27.1803 s.

**** AMSD: Mixed-Signal Activity Statistics ****
Number of A-to-D events:                       0
  Number of A-to-D events in IEs:              0
Number of D-to-A events:                       0
  Number of D-to-A events in IEs:              0
Number of VHDL-AMS Breaks:                     0
Number of direct digital accesses:               0

Total time required for tran analysis `tran': CPU = 32.1381 s, elapsed = 27.1962 s.
Time accumulated: CPU = 33.4399 s, elapsed = 28.5466 s.
Peak resident memory used = 123 Mbytes.

finalTimeOP: writing operating point information to rawfile.

Opening the PSF file ../psf/finalTimeOP.info ...
modelParameter: writing model parameter values to rawfile.

Opening the PSF file ../psf/modelParameter.info ...
element: writing instance parameter values to rawfile.

Opening the PSF file ../psf/element.info ...
outputParameter: writing output parameter values to rawfile.

Opening the PSF file ../psf/outputParameter.info ...
Simulation complete via transient analysis stoptime at time 39999999 FS

Aggregate audit (9:02:28 AM, Tue Aug 31, 2021):
Time used: CPU = 33.5 s, elapsed = 28.7 s, util. = 117%.
Time spent in licensing: elapsed = 18.4 ms.
Peak memory used = 125 Mbytes.
Simulation started at: 9:01:59 AM, Tue Aug 31, 2021, ended at: 9:02:28 AM, Tue Aug 31, 2021, with elapsed time (wall clock): 28.7 s.
spectre completes with 0 errors, 1 warning, and 10 notices.
xmsim: Memory Usage - Final: 50.6M, Peak: 53.9M, Peak virtual: 360.9M
xmsim: CPU Usage - 22.9s system + 35.2s user = 58.1s total (30.9s, 100.0% cpu)
TOOL:	xrun(64)	20.03-s007: Exiting on Aug 31, 2021 at 09:02:28 CEST  (total: 00:00:45)

Bjorn

Andrew Beckett over 4 years ago in reply to Bjorn VB

Hi Bjorn,

This is going to be quite difficult to debug without seeing it - the settings look the same as far as I can see from the log files. The versions used, simulation options and transient settings appear to be the same, and nothing that obvious jumps out. Can you contact customer support?

One difference I did notice was this:

Notice from spectre during initial setup.
2 vsources are short because their absolute value is less than or equal to 'vabsshort'.
Fast APS Enabled.

or spectre, whereas with AMS, it says:

Notice from spectre during initial setup.
1 vsources are short because their absolute value is less than or equal to 'vabsshort'.
Fast APS Enabled.

Can you show the three voltage sources in the netlist (maybe for both AMS and Spectre) so I can check if that might explain it?

Regards,

Andrew
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Andrew Beckett over 4 years ago in reply to Bjorn VB

Hi Bjorn,

This is going to be quite difficult to debug without seeing it - the settings look the same as far as I can see from the log files. The versions used, simulation options and transient settings appear to be the same, and nothing that obvious jumps out. Can you contact customer support?

One difference I did notice was this:

Notice from spectre during initial setup.
2 vsources are short because their absolute value is less than or equal to 'vabsshort'.
Fast APS Enabled.

or spectre, whereas with AMS, it says:

Notice from spectre during initial setup.
1 vsources are short because their absolute value is less than or equal to 'vabsshort'.
Fast APS Enabled.

Can you show the three voltage sources in the netlist (maybe for both AMS and Spectre) so I can check if that might explain it?

Regards,

Andrew
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Bjorn VB over 4 years ago in reply to Andrew Beckett

Hi Andrew,

Thank you for looking into my problem. As I was also debugging while generating these log files. I changed the cds_thru with 0V vdc sources. which causes the notices in the log file.
I changed them back to cds_thru and now the notices are gone for both the AMS as well as the spectre sim. Still, the difference is there.

Because I cannot share the netlists because of confidentiality, I will contact customer support.

Thank you for your time.

Kind regards,

Bjorn
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ShawnLogan over 4 years ago in reply to Bjorn VB

Dear Bjorn,

Thank you for posting the output log files and your version information! I am finally able to study them and apologize for my tardy response. I did notice something else and have a couple of suggestions. If you are still interested, my comments and suggestions follow. I understand you are contacting customer support and may not be motivated to review and comment on my thoughts and fully understand as I do not want to waste any of time.

1. In your two log files, the maximum node voltages and maximum terminal currents are different - which may provide some insight into the apparent differences you report in VCO frequency. Specifically, in your AMS log, the maximum node voltage and maximum terminal current is:

Maximum value achieved for any signal of each quantity:
V: V(ringosc.ring[49]) = 1.275 V
I: I(ringosc.V2:p) = 885.2 uA

In your spectre simulation log the corresponding maximum node voltage and maximum terminal current is:

Maximum value achieved for any signal of each quantity:
V: V(I1<48>.MU1_0-M_u3_turbo_m4:int_g) = 1.278 V
I: I(V0:p) = 2.612 mA

a. It appears the maximum voltages are similar and, perhaps, each node may represent the drain of the same ring oscillator inverter. Is this the case? If so, I would think it would be instructive to viewing and compare of these nodes as a function of time.

b. Interestingly enough the maximum terminal currents from the voltage source V0 p terminal in spectre, but the p terminal of ringosc.V2 in your AMS simulation. Please consider why the currents are so different and, to me, appear to be different terminals in the netlist. Is it possible to plot these two currents? My experiences suggest that to accurately assess terminal currents, a higher level of simulation accuracy than "moderate" is required. Comparing the two currents in ViVA might provide some insight into the accuracy of the currents.

c. If the comparison of the two currents does suggest there may be an accuracy issue to you, I might suggest you consider re-running each simulation using an errpreset of "conservative" in lieu of "moderate" and then compare the two currents from this increased accuracy set of simulations to determine if the currents now appear different than those in the moderate simulations and, more importantly, if the two maximum reported terminal currents of the simulation are closer in value than 2.612 mA and 885.2 uA shown in your moderate output logs.

2. How are you measuring the VCO frequency?

a. Are you including any of the start-up portion of the waveforms in your frequency measurement?

b. Are you are using the frequency() function? Consider using the Calculator freq() function - not the frequency() function, on the ring oscillator output node and make sure the threshold to measure the frequency is close to the supply voltage/2 for single ended waveforms. Plot the frequency of the two oscillators as a function of time. Are the frequencies of the two simulation results closer at the end of your simulation (for example, the last few nanoseconds of your 40 ns simulation time)?

c. Does it appear the VCO frequencies are each close to being settled near the end of your simulation (i.e., the change in frequency versus time near 40 ns is relatively small)? How similar or different are the two VCO frequencies over the 40 ns simulation time?

3. Consider simplifying your transient simulation and then compare the frequencies of each VCO at the end of each 40 ns simulation.

a. I would suggest a set fo simulations where you disable transient noise and perform a conventional non-transient noise simulation using each simulator and compare the frequency results to your transient noise based simulation. Being ring VCO, their frequency will be extremely sensitive to the presence of noise and I am trying to understand if the differences you are observing may be related to your use of a transient noise simulation.

You may have already considered these items Bjorn, and if so, I apologize! However, my study of your simulation logs brought these thoughts to mind and I felt I should at least mention them.

Shawn
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Bjorn VB over 4 years ago in reply to ShawnLogan

Hi Shawn,

I performed the suggestions you proposed.

1. I changed the simulation to not simulate with transient noise. I also changed from using a cds_thru instance to connect my vss net and the gnd! net to using a regular gnd symbol. This results in an even more simple circuit. In the logs, the max value achieved is now the same for both simulations (885.2 uA). the simulations are also done with conservative errpreset.

2. I was indeed measuring the ring oscillator's frequency with the frequency() function. Changing to the freq() function and looking to the frequency vs time there are no frequency transients.

3. The ring oscillator can not be tuned by a control voltage. It is just a ring of 51 inverters. For both simulations, an initial condition is set to one node to make the ring start oscillating immediately.

I also have looked into the initial conditions files (spectre.ic) for both simulations which match almost exactly.

Kind regards,

Bjorn
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Bjorn VB over 4 years ago in reply to Bjorn VB

Hello,

We found our problem. The difference in frequency was due to a difference in the included sections in the model file of our technology.

Using the spectre simulator, a pre_layout section was enabled by default, causing to add additional estimated capacitance and resistance to the devices.
When switching to the AMS simulator this section was not included anymore resulting in faster devices.

Thanks a lot for everyone spending time to look into this problem.

Kind regards,

Bjorn
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ShawnLogan over 4 years ago in reply to Bjorn VB

HI Bjorn,

Thank you for even taking the time to read and try my few suggestions - but what is most important - is that you uncovered a device modeling difference! Great! Thank you for letting us know!

Shawn
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