Verilog Stimulus file

That example is for the end-of-lifed (and now removed) spectreVerilog flow - so it's using the very old mixed-signal simulation solution that dates from before AMS Designer (which has been around for 20 years or so).

You must have selected a different simulator at step 5:

5. From the SIMW, choose the spectreVerilog simulator with Setup->Simulator/Directory/Host.

because spectreVerilog doesn't exist.

Anyway, I did some experiments and made it work with a few changes here and there:

1. First of all, in step 5, pick "ams" as the simulator. 
2. For step 9, take the modified stimulus shown below and store in a file called "test.v" (put it in the working directory). This has been changed to directly reference the signal names rather than being mapped by ADE to do the same.Then:
   1. Simulation->Options->AMS Simulator and go to the Include Option Setting at the top of the Main tab. Press this button, and add test.v into the Files on xrun command line section.
   2. Further down on the Main tab (at the bottom) click on the Additional Arguments button and add "-top test" to the xrun arguments. This tells it to pick up the test module to drive the signals in the testbench
3. Before running the simulation in step 11, do step 12 to ensure the right signals get saved - otherwise you may not be able to plot them)
4. Before running the simulation in step 11, go to Setup->Connect Rules/IE Card and then on the "global" line change the supply voltage from 1.8 to 5 (this is a 5V design)
5. Also before running the simulation, edit the properties for the two capacitors I32 and I34 and remove the initial condition (set to 2.4V on both cases). It doesn't seem to work very well with this.
6. Change the stop time in step 10 to 20u rather than 5u

Then if you run the simulation, you'll see the VCO input frequency settling.

The testbench code is here:

// timescale set according to user specification in the STL deftiming statement

`timescale 100ps / 100ps

module test;

//	reg [#/in_ref];

//	top top([#/feed_back],[#/in_ref]);

   initial
   begin
      $monitor("%d  in_ref=%b  feed_back=%b  up=%b  down=%b\\nout4=%b  out5=%b  out2=%b  out9=%b",
$time, top.in_ref, top.feed_back, top.up, top.down,
top.out4, top.out5, top.out2, top.out9);

      force top.in_ref = 0;	/* net in_ref */
      force top.feed_back = 0;	/* net feed_back */
      force top.out2 = 1;	/* net out2 */
      force top.out4 = 0;	/* net out4 */
      force top.out5 = 0;	/* net out5 */
      force top.out9 = 1;	/* net out9 */
      #620  release top.feed_back;
	    release top.out2;
	    release top.out4;
	    release top.out5;
	    release top.out9;
   end

   always begin
      #1000 force top.in_ref = 1;
      #1000 force top.in_ref = 0;
   end
endmodule

Andrew

Thanks Andrew

Sorry for the late reply. The changes you proposed worked perfectly

Yes, I'd failed to say that I had changed the simulator to ams.

Indeed the tutorial is a bit old. Is it there an updated tutorial for the mixed-signal simulation I can reference for future use?

Again, thanks for the fantastic support

Regards,

ebarajas

This is a good place to start: Where to find good information on AMS Designer Simulations for new users - there are some (slightly old, but still for AMS) tutorials in the IC installation in the <ICinstDir>/tools/dfII/samples/tutorials/AMS directory (there's a PDF - mostly talking about the OSS/irun flow, which is now replaced by UNL/xrun but I think it would be close enough). These are also referenced on the page I linked to above.

Andrew