Can I pass a variable from ADE Explorer into a systemverilog module as an integer?

Hello,

I'd like to do some variable sweeps in which I declare a variable in ADE Explorer and have that variable pass directly into a systemverilog module to change some of the bit widths.  I'd like to set an integer bit width to a variable using hierarchical syntax.   Does anyone know if there's a way to do this?

Here's a couple of my failed attempts:

ATTEMPT #1

// Inside systemverilog module:

localparam NUM_BITS = cds_globals.NUM_BITS_VAR;
wire [NUM_BITS:0] my_wire;

// In ADE Explorer:
NUM_BITS_VAR set to 2 in ADE Explorer

==> result xmelab: *E,NOTDOT (<path name to verilog file>): Hierarchical name ('cds_globals.NUM_BITS_VAR') not allowed within a constant expression [4(IEEE)].

ATTEMPT #2

// Inside systemverilog module:
wire [cds_globals.NUM_BITS_VAR:0] my_wire;
|
==> result xmelab: *E,NOTDOT ( Hierarchical name ('cds_globals.NUM_BITS_VAR') not allowed within a constant expression [4(IEEE)].

VERSION INFO:

% virtuoso -V

@(#)$CDS: virtuoso version ICADVM20.1-64b 06/29/2021 18:30 (cpgsrv11) $

% virtuoso -W
sub-version ICADVM20.1-64b.500.19

Thank you,

Bill Huff