Accuracy / Resolution of real variable in SV - AMS simulation beeing limited to 6 bit ?!?!!

Hi Joachim,

This is the vdelta parameter for the E2R connectmodule. The default is normally vsup/64 so it's discretized into 64 steps (it has to be discretized because a change in voltage on the electrical side needs to be converted into an event on the real side (whilst the reals are continuous in value, they are discrete in time - clearly you cannot have an event on a continuous-time signal - it has to be triggered at some level).

If running from ADE, you can control this via the Setup->Connect Rules/IE Setup form - either the Extended tab of the Advanced Setup for IE Card, or the Customize button for the connectmodule if using the older Connect Rules/Connect Module Based Setup.

Regards,

Andrew.

Hi Joachim,

This is the vdelta parameter for the E2R connectmodule. The default is normally vsup/64 so it's discretized into 64 steps (it has to be discretized because a change in voltage on the electrical side needs to be converted into an event on the real side (whilst the reals are continuous in value, they are discrete in time - clearly you cannot have an event on a continuous-time signal - it has to be triggered at some level).

If running from ADE, you can control this via the Setup->Connect Rules/IE Setup form - either the Extended tab of the Advanced Setup for IE Card, or the Customize button for the connectmodule if using the older Connect Rules/Connect Module Based Setup.

Regards,

Andrew.

Dear Andrew,
I can not count how often your comments in the forums helped me before in the past 20 years. But this one really really nailed it!

I was hunting this down for 5 days in a row and because I used a similar setup before, which worked fine, I thought the error was in my SV code. I was not aware that meanwhile also the Cadence environment changed and I believe they switched from traditional connect lib to E2R connectmodules. 
Since I want to simulate an ADC with 15 bit resolution, I set it to vsup/65536 and suddenly just like magic, my distorted spectrum is now -100dB clean. And my own code is fine.

I am really surprised that even after I found out that this quantization was there and killing me, I was not able to google it or find it in the forums or the Cadence help. I even predicted that it must be 6 bit = 64 like I wrote in the header of the thread. But I was not able to find any reference to it. It must have hit many people before... Why is it set so low?? setting it to 2^16 did not change the simulation time for me.

Anyway, Andrew, THANK YOU SO MUCH, I can't express how much of a help your hint has been to me. It is HUGE! 
You are a star !
Thanks so much, you saved my weekend and probably my life :-))

Cheers and all the best,

 Joachim

Hi Joachim,

Thanks for the positive review!

I'm not really certain why the (somewhat arbitrary) decision of 64 levels was made - it was probably just a cautious "don't over-do it" choice to avoid a ton of events at the analog/digital boundary. We'd then have the usual problem of if we then change it, it's going to affect existing setups and that's then going to cause problems for some customers. The usual difficulty of changing anything at all once something is out in the wild for any length of time. I think in a simple case it wouldn't make much difference, but if you have many electrical/real interfaces it could get rather expensive - and if the real number model doesn't need that much resolution (which it might not in many applications) it's just going to slow things down. Unfortunately there's no single right answer here...

Anyway, glad to have helped, and have a good weekend!

Andrew