Stats

  • Locked Locked
  • Replies 4
  • Subscribers 64
  • Views 15875
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Extraction failure for Verilog-A due to for loop

UniFleSou

Hello, 

I was trying to implement a digital controlled oscillator model in Verilog-A. When I extract it, the extraction would fail (TE-4309). The code looks like this:

`include "constants.vams"
`include "disciplines.vams"
`define MATH_PI 3.14159265358979323846264338325790288419716

module DCO_VA_MODEL ( DIN, GND, CLK_OUT ) ;
input [7:0] DIN ; // little endian, DIN[0] is LSB
input GND ;
output CLK_OUT ;
electrical [7:0] DIN ;
electrical GND, CLK_OUT ;
// Parameter definition
parameter real freq_center = 1G ; // Hz
parameter real freq_range = 800M ; // Hz
parameter real vdd_supply = 1 ; // volt
parameter real din_center = 127.5 ; // LSB
// Variables for calculation
real din_digit ;
real freq_inst ;
real phi ;
real delta_phi ;
real cycle_count ;
integer i ;

analog begin
// calculate DIN in LSB
for (i=0; i<8; i=i+1) begin
din_digit = din_digit + ceil( V(DIN[i], GND) - vdd_supply/2 ) * pow(2,i) ;
end

din_digit = ( din_digit - din_center ) / pow(2,8) ;

// calculate the phi as if running at center frequency
cycle_count = freq_center * $abstime ;
phi = 2 * `MATH_PI * ( cycle_count - floor(cycle_count) ) ;

// calcualte the deviation in fet due to vin is not at the center
delta_phi = 2 * `MATH_PI * freq_range * idt( din_digit, 0 ) ;
V(CLK_OUT,GND) <+ vdd_supply/2 + vdd_supply/2 * sin(phi+delta_phi) ;

// set the simulation step
freq_inst = freq_center + freq_range * din_digit ;
$bound_step(0.04/freq_inst) ;
end

endmodule

I was able to determine that the issue has to do with the for loop since the code can be extracted without it. If I take the line in the for loop out of it and give i an integer value, the code can extract as well. I was wondering if anyone else could kindly point out my mistake?

  • If you'd hovered over the red highlighted region, or looked at the View->Parser Log File you'd have seen that it said:

    Error found by spectre during AHDL compile.
    ERROR (VACOMP-1192): "din_digit = din_digit + ceil( V(DIN[i], GND)<<--? -
    vdd_supply/2 ) * pow(2,i) ;"
    "/export/home/andrewb/support/forum/mylib/DCO_VA_MODEL/veriloga/veriloga.va",
    line 27: The index that accesses bits of the analog signal vector `DIN'
    is not a constant, constant expression, genvar variable, or
    genvar-constant expression. Use only a constant, constant expression,
    genvar variable, or genvar-constant expression to access bits of an
    analog signal vector.

    You simply need to change the line:

    integer i;

    to 

    genvar i;

    By the way, since you're including "constants.vams" you could have just used M_PI rather than defining your own MATH_PI (with more digits than would help, since you only have about 15-16 digits of precision in double-precision floating point numbers).

    Regards,

    Andrew

  • in reply to Andrew Beckett

    Hello Andrew,

    Thank you for your help. I was able to fix the code with your advice. 

    However, I think there is something wrong with the way I was configuring cadence virtuoso. When the veriloga extraction failed, I wasn't able to see any red highlights in my code, and when I do "View->Parser Log File", the command window just says "*WARNING* (TE-5003): No parser log file was found for '0XT_ADPLL_PROJ DCO_8B_VA_MODEL veriloga'. Use the 'Check' or 'Extract' commands to parse this cellview." This makes code writing and debugging more difficult. Still, I was able to run simulation with the veriloga model in spectre simulation. Could you advise me on how I may solve this issue? (Should I create a separate post for this?)

    In case this is needed, I was using Virtuoso ICADVM201HF and SPECTRE201HF. Here is the part of .bashrc file relating to cadence. 

    ################################################################################
    # Cadence
    ################################################################################
    CADENCEVER=ICADVM201HF
    SPECTREVER=SPECTRE201HF
    export CDS="/cad/cds/$CADENCEVER"
    export PATH=$PATH:/cad/cds/$CADENCEVER/tools/bin:/cad/cds/$CADENCEVER/tools.lnx86/dfII/bin
    export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/cad/cds/$CADENCEVER/tools/lib:/cad/cds/$CADENCEVER/tools/verilog/bin
    export CDS_LIC_FILE=[REDACTED]
    export CDSHOME="/cad/cds/$CADENCEVER"
    export MMSIMHOME="/cad/cds/$SPECTREVER"
    export CDS_Netlisting_Mode=Analog

    ######################################################
    # Spectre
    ################################################################################
    export SPECTRE_MODEL_PATH="$GF_PDK_HOME/Models/Spectre/models"
    export PATH=/cad/cds/$SPECTREVER/tools.lnx86/spectre/bin:$PATH
    export CDS_AUTO_64BIT=ALL

    export SPECTRE_DEFAULTS=-E
    export CDS_LOAD_ENV=CSF CWDElseHome

    Thank you and happy new year!

  • in reply to UniFleSou

    There are a couple of odd things in your settings above, but I don't think any of them would cause the problem (I tried setting up my environment in a similar fashion but couldn't reproduce it). The specific points I had about the environment are:

    1. You don't need to set LD_LIBRARY_PATH and certainly not include tools/verilog/bin in that path
    2. Usually you'd add either /cad/cds/$SPECTREVER/bin in the path or maybe (if you need to support very old versions of MMSIM) /cad/cds/$SPECTREVER/tools.lnx86/bin . I wouldn't include tools/spectre/bin (the world won't end, but it's not a recommendation)
    3. It's slightly unusual to have -E specified as a SPECTRE_DEFAULT

    I wonder whether it might be an issue with the specific versions used (ICADMV201HF and SPECTRE201HF aren't very specific). What does "virtuoso -W" and "spectre -W" report in the terminal window?

    Thanks,

    Andrew

  • in reply to Andrew Beckett

    I feel really stupid for saying this, but I forgot to give myself write permission to the ".cadence" folder in the work directory when I copied it from the PDK files. Giving myself full read/write permission to the ".cadence" folder and everything in it solved the issue I mentioned. 

    Thank you again for your kind help!

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.