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verilog AMS sine wave generator

 Re: Verilog AMS sine generator
Reply #2 - Today at 1:03am
    
Hi ,
 I have created a wrapper around my  .vams netlist of an anlog circuit. I want to drive a signal as an input from the digital domain to my analog netlist hence I created a wrapper.
The input to the wrapper is a frequency ,phase and amplitude but I want to drive a sine wave as input to my analog netlist, hence I am creating this in my wrapper and trying to feed that as input to my vams netlist as it needs a signal as an input.

This is the part of the code which I need help with:
electrical      bbmux_lp_n_ai;
 electrical      bbmux_lp_p_ai;
 electrical      lp_n_ai;
 electrical      lp_p_ai;
 
 real       offset = 2.5;
 
 assign  bbmux_lp_n_ai = offset + (bbmux_lp_n_ai_amplitude * $cos(2*3.14159265358979323846*bbmux_lp_n_ai_frequency*$abstime));
 assign  bbmux_lp_p_ai = offset + (bbmux_lp_p_ai_amplitude * $cos(2*3.14159265358979323846*bbmux_lp_p_ai_frequency*$abstime));
 assign  lp_n_ai = offset + (lp_n_ai_amplitude * $cos(2*3.14159265358979323846*lp_n_ai_frequency*$abstime));
 assign  lp_p_ai = offset + (lp_p_ai_amplitude * $cos(2*3.14159265358979323846*lp_p_ai_frequency*$abstime));
 

 
 
   // Instantiate the analog netlist
 rxbb_lp rxbb_lp_inst(
   .bbmux_lp_n_ai(bbmux_lp_n_ai) ,
   .bbmux_lp_p_ai(bbmux_lp_p_ai) ,
   .lp_n_ai(lp_n_ai) ,
   .lp_p_ai(lp_p_ai)
);
I also tried creating a seprate function as shown in the guide:
electrical g, gnd;
wire bbmux_lp_n_ai;
wire bbmux_lp_p_ai;
wire lp_n_ai;
wire lp_p_ai;

vsine #(.dc(0), .ampl(1.3), .freq() bbmux_lp_n_ai (g, gnd);
vsine #(.dc(0), .ampl(bbmux_lp_p_ai_amplitude), .freq(bbmux_lp_p_ai_frequency)) bbmux_lp_p_ai (g, gnd);
vsine #(.dc(0), .ampl(lp_n_ai_amplitude), .freq(lp_n_ai_frequency)) lp_n_ai (g, gnd);
vsine #(.dc(0), .ampl(lp_p_ai_amplitude), .freq(lp_p_ai_frequency)) lp_p_ai (g, gnd);







  // Instantiate the analog netlist
 rxbb_lp rxbb_lp_inst(
   .bbmux_lp_n_ai(bbmux_lp_n_ai) ,
   .bbmux_lp_p_ai(bbmux_lp_p_ai) ,
   .lp_n_ai(lp_n_ai) ,
   .lp_p_ai(lp_p_ai)
);



endmodule


module vsine(ampl,freq,phase,out);
input ampl;
input freq;
input phase;
output out;
voltage out;
real freq, ampl,phase;
parameter real offset=0.0;
analog begin
v(out) <+ ampl*sin(2.0*‘M_PI*freq*$abstime) + offset;
$bound_step(0.05/freq);
end
endmodule
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