Instantiating a schematic in a verilog-a module

Yes, this should work. You will need a symbol view for the schematic being instantiated, and you'll need to "check and save" (or "build and extract" to use the right terminology) for this to work.

Which simulator? Which IC and simulator sub-versions are you using?

Andrew

I have checked and saved, but I can't make it work.

Which simulator? 

As far as I know I am using Spectre.

Which IC and simulator sub-versions are you using?

No idea, where can I get this information? 

Let me explain in more detail what I have done so far, maybe you can see the flaw in my workflow.

In my library I have a cell called inverter with a schematic and a symbol. I have also defined some CDF parameters, to easily change the dimensions and the multiplicity of  the transistors. 

I also have the ring_oscillator defined as follow

Moreover, have defined a ring_oscillator symbol and I have instantiated it in a testbench. When I run the spectre transient simulation I get the following errors:

The instance `I0' is referencing an undefined model or subcircuit, `inverter'. Either include the file containing the definition of `inverter', or define `inverter' before ru
nning the simulation.
The instance `I1' is referencing an undefined model or subcircuit, `inverter'. Either include the file containing the definition of `inverter', or define `inverter' before ru
nning the simulation.
The instance `I2' is referencing an undefined model or subcircuit, `inverter'. Either include the file containing the definition of `inverter', or define `inverter' before ru
nning the simulation.

summarizing here is my file structure:  

wk_dantecpp (library)   
│
└───inverter (cell)
│      schematic
│      symbol  
│   
└───ring_oscillator 
| veriloga
| symbol
|
└───tb_ring_oscillator
 schematic

Thanks, I really appreciate your help. 

To find the version of Virtuoso, use Help->About in any Virtuoso window - or type "virtuoso -W" from the UNIX command line, or getVersion(t) in the CIW. For Spectre, this should appear near the top of the simulation log, or you can type "spectre -W" from the UNIX command line.

I just tried this in IC6.1.8 latest hotfix (.500.23), but this should work in pretty much any version. When I create the Verilog-A and do the "Build a database of instances..." icon (or File->Extract) - as highlighted here:

then I get the three inverters showing in the navigator (assuming I've clicked on instances) and in the CIW I see:

veriloga Diagnostics: Warnings exist in veriloga text of cell ring_oscillator.
Reading file:
/export/home/myname/support/forum/wk_dantecpp/ring_oscillator/veriloga/veriloga.va
Reading file:
/export/home/apps/SPECTRE201_isr/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading file:
/export/home/apps/SPECTRE201_isr/tools.lnx86/spectre/etc/ahdl/disciplines.vams
******************************************
Structure summary for module "ring_oscillator"

child bound to (library view)
--------------------------------------
I0 (wk_dantecpp - view symbol)
I1 (wk_dantecpp - view symbol)
I2 (wk_dantecpp - view symbol)
******************************************
(TE-4308): Extract completed for cellview 'wk_dantecpp ring_oscillator veriloga'

As you can see, it found the symbol.

Note I did change the inverter instances (that wasn't needed to fix this but the circuit wouldn't work with it as-is). You had the instances with the connections passed by order, rather than by name. The trouble is that the order of the inverter connections was unlikely to be well-defined (perhaps you could have edited the termOrder in the CDF for the inverter, but that seems unnecessarily complicated to me when the language supports connect-by-name).

I've attached a tarball of a library (I called everything the same as you did, but it's using transistors from gpdk045). I have the simulation setup in wk_dantecpp/tb_ring_oscillator/maestro (ADE Explorer) and it requires $KITHOME to be set to point to where gpdk045 (can be found at http://pdk.cadence.com) to pick up the models. This all works perfectly...

Regards,

Andrew

https://community.cadence.com/cfs-file/__key/communityserver-discussions-components-files/92/wk_5F00_dantecpp.tgz

here is my version

I followed all your steps and I see the instances in the navigator, 

******************************************
Structure summary for module "ring_oscillator"

child bound to (library view)
--------------------------------------
I0 (wk_loid_ic_c11hv - view symbol)
I1 (wk_loid_ic_c11hv - view symbol)
I2 (wk_loid_ic_c11hv - view symbol)
******************************************
(TE-4308): Extract completed for cellview 'wk_loid_ic_c11hv ring_oscillator veriloga'

however, I keep getting the same error at runtime. It seems like the simulator is not reading the path where the inverter is defined. Unfortunately, I cannot upload your working example in my work environment. 

Best,

Dante 

Dante,

The simulator wouldn't look in that path, but I'd expect the netlister to traverse into the inverter and netlist (assuming that the config or switch/stop view lists are set up correctly).

I'm not sure whether you are simulating in ADE with a config view or starting from the top level schematic, but one thing to check is that if it's a config you don't have 'veriloga' in the stop list, and similarly under Setup->Environment if the top level is a schematic, you don't have veriloga in the stop list on that form.

If that doesn't help I suggest you contact customer support - looking at it will be quick (if you do this, please mention in the text of the case that you submit that I've suggested logging a case and that it can be assigned to me - please include a link to this post). Looking at the paths in your netlist I think you're from a normal customer rather than an academic institution, so that shouldn't restrict your access to our support portal (sometimes for academic customers only limited users can log support cases).

Regards,

Andrew

Andrew Beckett said:

one thing to check is that if it's a config you don't have 'veriloga' in the stop list

That was it!

Best,

Dante 

Andrew Beckett said:

one thing to check is that if it's a config you don't have 'veriloga' in the stop list

That was it!

Best,

Dante