How to include a verilog file/functional view in HED?

Hi all

I'm doing an AMS simulation and I'm instantiating a block whose definition is included in a Verilog file and also a functional view. In the HED, I can't define a hierarchy beneath a functional view.

How can include that file definition?

Thanks

Please do not post the same question in multiple forums (see the forum guidelines). It won't necessarily get answered any quicker - usually the opposite because it creates more work... 

This time I've joined the two posts rather than deleting them both.

It's not clear what you mean. What does it mean by "I'm instantiating a block whose definition is included in a Verilog file and also a functional view"? Where are you instantiating it? You can certainly have hierarchy beneath a functional view and you should be able to view switch using HED.

Perhaps contacting customer support would be best?

Andrew

For example, I have the following verilog created as a functional view in Virtuoso:

module SRAM_BLOCK
#(parameter WIDTH_INPUT=64, WIDTH_OUTPUT=4,WIDTH_DATA=8)
(
input clk_fifo_i,
input rst_mst_i,
input eval_i,
input [7:0] cmp_i,
input [WIDTH_DATA-1:0] counter_i,
input load_fifo_i,
output [WIDTH_OUTPUT-1:0] SO
);

DESER_FIFO64 I_DESER ( clk_fifo_i, DATA[WIDTH_INPUT-1:0], rst_mst_i, load_fifo_i, SO[3:0]);

endmodule

In my HED I will have the stopped view configured to functional, but spectre is reporting me the following error:

SRAM_BLOCK:module' was set to be stop view in Cadence Hierarchy Editor(HED) but this instance has hierarchy beneath it. Review and update its settings in HED appropriately

I have to add somehow the DESER_FIFO64 definition. I have tried `include statement without success. 

How can I do it from HED? 

Thanks 

Why are you setting the functional view to be a stop view? It's not a stop view! You want the hierarchy expanded beneath it, so it makes no sense to make it a stopping view.

Andrew

By the way, the function of the Stop View List is explained at https://support.cadence.com/apex/techpubDocViewerPage?path=assembler/assemblerIC6.1.8/asmNetlisting.html#pgfId-1024871 

Hi Andrew and Frank.

I have found the issued Verilog portion :

genvar i;

generate
for (i=0; i<7; i=i+1) begin
SRAM I_SRAM( rst_mst_i, eval, counter_i[7:0], cmp_i[i], DATA[8*(i+1)-1:8*i]);
end
endgenerate

Using generate statement, HED is unable to descend into SRAM hierarchy.

How can I work around it?

Thanks

This unfortunately is a known limitation. The main issue is that generate blocks are parameterised connectivity and that cannot really be represented in parent-child database that HED uses. The workaround is to add a reference to the external file with the definition of the SRAM in the Verilog-AMS options.

Andrew

... as explained at https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000006DdhMUAS