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The SNR of real signals are degrading in system Verilog model compare to analog signals

bikram1994

Hi

The SNR of real signals are degrading in system Verilog model compare to analog signals.

Am I missing anything in the setup or in the code?

Can I improve the SNR of real signal inside system Verilog model?

Please help me.

 

Here I have put the test bench and all .

Test Bench:

config:

Vinm:

                                                                 

vinp:

Code: SystemVerilog

//systemVerilog HDL for "ProjA1_AMS_tb", "INP_Check_sv" "systemVerilog"

`timescale 1ns / 1ps

module INP_Check_sv

(

input logic clk_5p4Ghz, //5.4Ghz clock

input real adc_in1 , // Signal time samples

input real adc_in2 , // Signal time samples

output bit [1:0] adc_out

);

real inp;

assign inp=(adc_in1-adc_in2)/2;

endmodule

 

 

 

Spectrum of vinp:

SNR=226.74dB

Spectrum of adc_in2:

SNR=52.7dB

 

 

 

 

 

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