Module instance name changed to hdl_xx when creating verilog netlist

The most likely explanation for this is that you have the same name used for different objects (e.g. the same cell name in more than one library, or you have a config view and have picked multiple views of the same cell). The error message is rather misleading (I agree) because that's not an illegal name. I was able to create a schematic using that name and it didn't map it.

You didn't mention which tool version you're using, but I think this has been the standard behaviour for some time.

Perhaps you should contact customer support so that an application engineer can look at it with you. If you do so, please mention this thread (and also CCR 2361289 which discusses a similar issue).

Regards,

Andrew

Thanks Andrew - for the effort ! 
This problem mistrialsly disappear after I did some changes in the config view I use(unrelated with the issue above) .

Not sure exactly how and why - but Im pretty sure you  right it is related with something wrongly defined in the config.   

(this config details mysteries - way deep up in the hierarchy tree can be so annoying sometimes ... its a place some kind of  SRC C&S implementation for config - can be useful - just  a small wish which may be raised up in the chain ).   

Thanks again . 
Yehuda.

YB36 said:

(this config details mysteries - way deep up in the hierarchy tree can be so annoying sometimes ... its a place some kind of  SRC C&S implementation for config - can be useful - just  a small wish which may be raised up in the chain ).

I'm not quite sure how the config could be "checked" given that it just defines a set of rules for hierarchy expansion. I don't know how it could know whether that's right or wrong because that's your decision as to what the intent is. 

Andrew

well - there are stuff that can be told to the user as warnings (at least)- such things that causes  this module name change. There are set of conditions being checked in the background and when they occur the software decide to do stuff such as changing the module name. For sure it means that something is not being well define in the config (my idea is to inform the user about the point being not well defined).
Another example is when  an instance group (something like buf<30:0> ) being partially defined as one view and partially as another. In such cases verilog netlist will not be able to be create - and for right reasons . But the issue is  - I dont know where in the hierarchy I made the mistake - so I need to go through all hierarchy tree and look where this error occur.         

The trouble is, none of that is really an issue with the config. The fact that the Verilog netlister need to rename one of the modules when either the same cellName appears in multiple libraries or you have different views of the same cell included is really a consequence of the fact that the Verilog language itself only distinguishes at the cell (module) level - and so it needs a different name in each of those cases. Something needs to be mapped. There's no way the hierarchy editor can know that you want to disallow multiple cells with the same name in different libraries or multiple views of the cell (in fact the latter is kind of the point of the hierarchy editor!).

The ability to bind differently different iterations of an iterated instances (such as buf<30:0>) was a much requested capability that was added relatively recently, but is restricted to just AMS simulations (support for other simulators would require extensive changes in the netlisting infrastructure and the primary driver for the request was always AMS). Since the hierarchy editor is not tied to the simulator used, it can't really know that this is a problem. Of course, it would be best if the Verilog netlister pinpointed the problem, and that's really what should happen in this case). I've not checked to see how that behaves, but if you're not happy with the reporting of the error from the Verilog netlister I would suggest you contact customer support to get it improved.

Andrew