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how to create a random seed in verilogams with $random

Pedro P

I am struggling to create a random seed in verilogams, I know how to create a random see in systemverilog, thats easy, but what about in verilog ams ?

I have created the following verilogams code, where the parameter seed=0 , and my expectation is that every-time i run this code i would get an initial seedx using $random , that should be different every-time based on the PID.

I see this in solution in multiple cadence documents, but the reality is whenever i run it I always get the same seedx , meaning that $random produces the same number at time 0 , in the initial block.

Can someone help me whit this ?

im using :

cadence 06.18.240

xcelium 21.09.007

spectre 21.10.303

------------------------------------------------

module ams (en);
input en;


// seed of 0 should give a random seed based on the PID
parameter integer seed = 0;

integer seedx;

initial begin
   seedx = (seed == 0) ? $random : seed; 
end

endmodule

  • I'm wondering why you think it should be based on the process id? The Verilog-AMS Language Reference manual (from Accelera) says:

    The random_seed argument may take one of several forms. It may be omitted, in which case the simulator picks a seed. If the call to $random is within the analog context, the random_seed may be an analog integer variable. If the call to $random is within the digital context it may be a reg, integer, or time variable. If the random_seed argument is specified it is an inout argument; that is, a value is passed to the function and a different value is returned. The variable should be initialized by the user prior to calling $random and only updated by the system function. The function returns a new 32-bit random number eachtime it is called.

    The system function $random shall always return the same stream of values given the same initial random_seed. This facilitates debugging by making the operation of the system repeatable.

    It doesn't say anywhere about the simulator-generated seed being different based on the process id (which would go against the last sentence).

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew I have found the LRM and for me it wasn't not 100% clear about the "The function returns a new 32-bit random number each time it is called" and so I thought was related to the PID.

    I noticed that in my example, where i use the $random in a digital context without (initialising the seed / passing a seed to the function) , that in my example I always get the same seedx value over and over again.

    in systemverilog I can use -svseed random , but in the case of verilogams , how can i get a way of generating a new random seed whenever I lunch a new simulation ? is there a way I could do that ?

    Thank you, Pedro.

  • in reply to Pedro P
    Pedro P said:
    Hi Andrew I have found the LRM and for me it wasn't not 100% clear about the "The function returns a new 32-bit random number each time it is called" and so I thought was related to the PID.

    Of course, the whole point of $random is that each time it is called (within a simulation) it returns a new 32-bit random number. It doesn't say anything that the sequence itself will be different from one invocation of the simulator to another.

    There's not (as far as I can find) any option to initialize the default seed from the command line for Verilog-AMS. Of course, you could use:

    $random(`AMSSEED)

    and then on the command line use -define AMSSEED=2 or similar.

    Andrew

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