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ERROR (HED-1073) and ERROR (OSSHNL-911) when simulating vhdl + analog blocks

delgsy

I am simulating a schematic containing vhdl+analog blocks.
This is the error I got when I try to generate the netlist if I choose behavioral or entity for the vhdl block in config.
The chosen simulator is ams.
Adding "ASSIGN <mylibName> TMP xxxxx/TMPxxx" does solve the issue.


I use the following software:
IC6.1.8
Spectre 19.1.0 64bit 12/11/2020 22:29 (csvcm36c-4)
XCELIUM 20.09
These 3 and other softwares are there when I execute echo $path.
Is there anything that I can try to solve this?


I found a (almost?) similar issue in this post.
I did not try creating hdl.var because I do not the content of it.

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