Apply Input to array in Cadence virtuoso

Dear AnubhaSehgal,

AnubhaSehgal said:

I have an schematic of array of 784 * 10 CMOS devices, I want to give different pulse voltage inputs (present in csv file format) to each device.

I apologize if I do not totally understand your intent...but my interpretation is that you have 784 instances of a subcircuit with the subcircuit containing 10 CMOS devices. You would like to simulate the 784 instances with the inputs to each of the 784 instances defined in a unique ".csv" file.

If my understanding is correct, suppose your create a test been with a single instance of your 10 CMOS device subciruit with a single vfpwl source driving the input of the subcircuit. I am assuming you are using a file based piecewise linear source that points to one of your 784 "csv" filenames.

If you choose the names of your 784 ".csv"  filenames such that they can be defined as a design variable, you can use an Assembler based simulation with the design variable swept between the name of the first and the last ".csv" file.

An example of how to set the filename a design variable, shown for an S-parameter simulation where the S-parameter file is swept, please take a look at the article on the Cadence On-line support site at URL:

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000006DdyOUAS&pageName=ArticleContent&oMenu=People%20who%20viewed%20this%20also%20viewed

I hope I understood your intent correctly!

Shawn

Hello.. 

Thanks for your feedback. But the question is slightly different. I have an array of CMOS devices (containing instances of 784 rows and 10 columns)  i.e. total of 7840 instances. I want to give pulse input to each instance, whose input values I have in single .csv format file. How can I give this input to each instance using verilog-A?