Asynchronous Ideal ADC in Verilog A in DC simulation

I am trying to hack the Ideal 8 bit ADC that comes in AHDL library so that on initial step it can find the output.

There is a funny thing going on with the sim. If I brute force in the initial statement: V(vd9) <+ 5;  on the first DC solution it sets vd9 to 5V and on next iterations it defaults to 0V. I am running 1C6.1.8-64b.500.17

I remember having this working in my old job where we had a newer version of Cadence. Any help will be great.

Code:

`include "discipline.h"
`include "constants.h"

module adc_10bit(vd9, vd8, vd7, vd6, vd5, vd4, vd3, vd2, vd1, vd0, vin, vclk);
electrical vd9, vd8, vd7, vd6, vd5, vd4, vd3, vd2, vd1, vd0, vin, vclk;
parameter real trise = 0 from [0:inf);
parameter real tfall = 0 from [0:inf);
parameter real tdel = 0 from [0:inf);
parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans_clk = 2.5;
parameter real vref = 1.0;

`define NUM_ADC_BITS 10
real unconverted;
real halfref;
real test;
real vd[0:`NUM_ADC_BITS-1];
integer i;
integer j;
analog begin

@ ( initial_step ) begin
halfref = vref / 2;
unconverted = V(vin);
for (j = (`NUM_ADC_BITS-1); j >= 0 ; j = j - 1) begin
vd[j] = 0;
if (unconverted > halfref) begin
vd[j] = vlogic_high;
unconverted = unconverted - halfref;
end else begin
vd[j] = vlogic_low;
end
unconverted = unconverted * 2;
end
V(vd9) <+ vd[9]; // Hacked in one case to be 5V - was only 5V on first run, went to 0V after that.
V(vd8) <+ vd[8];
V(vd7) <+ vd[7];
V(vd6) <+ vd[6];
V(vd5) <+ vd[5];
V(vd4) <+ vd[4];
V(vd3) <+ vd[3];
V(vd2) <+ vd[2];
V(vd1) <+ vd[1];
V(vd0) <+ vd[0];
end

@ (cross(V(vclk) - vtrans_clk, 1)) begin
unconverted = V(vin);
for (i = (`NUM_ADC_BITS-1); i >= 0 ; i = i - 1) begin
vd[i] = 0;
if (unconverted > halfref) begin
vd[i] = vlogic_high;
unconverted = unconverted - halfref;
end else begin
vd[i] = vlogic_low;
end
unconverted = unconverted * 2;
end
end

//
// assign the outputs
//
V(vd9) <+ transition( vd[9], tdel, trise, tfall );
V(vd8) <+ transition( vd[8], tdel, trise, tfall );
V(vd7) <+ transition( vd[7], tdel, trise, tfall );
V(vd6) <+ transition( vd[6], tdel, trise, tfall );
V(vd5) <+ transition( vd[5], tdel, trise, tfall );
V(vd4) <+ transition( vd[4], tdel, trise, tfall );
V(vd3) <+ transition( vd[3], tdel, trise, tfall );
V(vd2) <+ transition( vd[2], tdel, trise, tfall );
V(vd1) <+ transition( vd[1], tdel, trise, tfall );
V(vd0) <+ transition( vd[0], tdel, trise, tfall );

`undef NUM_ADC_BITS
end
endmodule