I am trying to simulate a verilog functional view, but it gives this error.
ERROR (OSSHNL-381): Missing or corrupt .oa file in cellview 'myLib/myCell/functional'. The OSS netlister can onlyprocess cellviews that have a valid .oa file. This file can be created byeither importing the cellview using tools like 'Verilog In' or 'VHDL IN', or byopening and writing the text file in the Library Manager.
I already disabled the OSS netlister using the below env setup. However it doesn't work for me.
asimenv.startup amsOSSNetlisterFlag boolean nil
Any help ?
Can you confirm your IC (Virtuoso) version?
I am using below.
getVersion()"@(#)$CDS: virtuoso version ICADVM20.1-64b 01/25/2022 18:41 (cpgsrv11) $"