Community Mixed-Signal Design Issue with simulating Verilog Functional view

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Issue with simulating Verilog Functional view

AmarDas

Hi,

I am trying to simulate a verilog functional view, but it gives this error.

ERROR (OSSHNL-381): Missing or corrupt .oa file in cellview 'myLib/myCell/functional'. The OSS netlister can only
process cellviews that have a valid .oa file. This file can be created by
either importing the cellview using tools like 'Verilog In' or 'VHDL IN', or by
opening and writing the text file in the Library Manager.

I already disabled the OSS netlister using the below env setup. However it doesn't work for me. 

asimenv.startup amsOSSNetlisterFlag boolean nil

Any help ?

Regards,

Amar

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