How to define current in verilogams-wreal model ?

If it's a wreal model then the output is just a variable - you assign it with the normal assignment operator (i.e. "=") rather than a contribution statement. Without seeing the details of your model, it's hard to be more specific.

Andrew

Hi Andrew,

Thank you for the response.

Let me explain the problem with an example.

Verilog-A code of this block:

`include "constants.vams"
`include "disciplines.vams"

module bias(en_1,en_2,VDD,VSS,V_out,I_out);

input en_1;

electrical en_1;

input en_2;

electrical en_2;

input VDD;

electrical VDD;

input VSS;

electrical VSS;

output V_out;

electrical V_out;

output I_out;

electrical I_out;

analog begin

if(V(en_1)>0.45) V(V_out) <+ 800m;

else V(V_out) <+ 0;

if(V(en_2)>0.45) I(I_out) <+ 2u;

else I(I_out) <+ 0;

end

ensmodule

verilogams_wreal model:

`include "constants.vams"
`include "disciplines.vams"

`timescale 1ns/1ps

module bias(en_1,en_2,VDD,VSS,V_out,I_out);

input en_1;

wreal en_1;

input en_2;

wreal en_2;

input VDD;

wreal VDD;

input VSS;

wreal VSS;

output V_out;

wreal V_out;

output I_out;

wreal I_out;

real ts;

initial begin
ts = (0.04 / 13G) * 1e9;
end

always #ts begin

if(en_1>0.45) V_out) = 800m;

else V_out =0;

if(en_2>0.45) I_out) = 2u;

else I_out = 0;

end

ensmodule

Here in verilogams-wreal model, can't we define voltage and current explicitly?

I didn't try your code, but there are some typos - you have some extra close parentheses:

if(en_1>0.45) V_out) = 800m;

else V_out =0;

if(en_2>0.45) I_out) = 2u;

else I_out = 0;

I think if you remove those, it should work.

Andrew