AMS netlister issue

Dear Forum,

I have an issue starting an AMS simulation. User A cant run the AMS simulation and has a netlist log file as shown below. User B can netlist and ALSO run the simulation successfully, his logfile is also shown below.

I see a difference in the way the toplevel cell is netlisted, in the working case it is mentioned as "Library ....... - schematic" in the failing case I see "Verilog-AMS ....." 

It feels like the netlister is configured differently for both users. Does anyone have a clue on how to fix this issue?

==== USER A  ========

// AMS netlist generated by the AMS Unified netlister
// IC subversion:  IC6.1.8-64b.500.6
// Xcelium version: 20.09-s010
// Copyright(C) 2005-2009, Cadence Design Systems, Inc
// User: xin43 Pid: 14088
// Design library name: IGNITE_AMS
// Design cell name: ignite_core_tb
// Design view name: config_ams
// Solver: Spectre

`include "disciplines.vams"
`include "userDisciplines.vams"
// HDL file - IGNITE_AMS, ignite_core_tb_CONTROL, systemVerilog_bringup.
// HDL file - IGNITE_AMS, ignite_core_tb_DRIVER, systemVerilog.
// Verilog-AMS cds_globals module for top-level cell:
//    IGNITE_AMS/ignite_core_tb.
// Generated by ADE.
// Cadence Design Systems, Inc.

==== USER B  ========

// AMS netlist generated by the AMS Unified netlister
// IC subversion: IC6.1.8-64b.500.6
// Xcelium version: 20.09-s010
// Copyright(C) 2005-2009, Cadence Design Systems, Inc
// User: vis41 Pid: 63953
// Design library name: IGNITE_AMS
// Design cell name: ignite_core_tb
// Design view name: config_ams
// Solver: Spectre

`include "disciplines.vams"
`include "userDisciplines.vams"
// HDL file - IGNITE_AMS, ignite_core_tb_CONTROL, systemVerilog_bringup.
// HDL file - IGNITE_AMS, ignite_core_tb_DRIVER, systemVerilog.
// Library - IGNITE_AMS, Cell - ignite_core_tb, View - schematc
// LAST TIME SAVED: Oct 10 14:50:45 2022
// NETLIST TIME: Oct 11 11:29:23 2022