SystemVerilog AMS simulation (ADE) xmelab ERROR, TYCMPAT: port or terminal connection type check failed on instance (expecting datatype compatible with 'packed array' but found 'unpacked array[0:1] of packed array [3:0] of logic' instead)

Hi, Andrew. Do you have any clue to fix this AMS elaboration issue? Thank you

ADJK said:

Hi, Andrew. Do you have any clue to fix this AMS elaboration issue? Thank you

I was going to take a quick look earlier (I have been doing the day job all day and haven't had a moment), and to be honest the fact that none of the example pieces of code have been shared as text meant that I deprioritised as I'd have to spend typing in four modules from pictures of the code. I'm much more likely to get to looking at something if it minimises the time it needs to do the basic setup to reproduce the problem and investigate it...

If you'd be willing to share the text for all four modules that will increase the chance of me having time to look at it tomorrow.

Andrew 

Sure. Here is the blocks I used.

Thank you.

///////////////////////////////////////////////

module inv_4b (
input [3:0] in,
output reg [3:0] out );

always @(*) begin
out = ~in;
end

endmodule

///////////////////////////////////////////
module inv_4b_v1 ( in, out );

input wire [3:0] in[2];
output wire [3:0] out[2];

assign out[0][3:0] = ~in[0][3:0];
assign out[1][3:0] = in[1][3:0];

endmodule

/////////////////////////////////////////////
module inv_4b_v2 ( in_0, in_1, out_0,out_1 );

input wire [3:0] in_0, in_1;
output wire [3:0] out_0,out_1;
wire [3:0] mid[2];

assign mid[0][3:0] = ~in_0[3:0];
assign mid[1][3:0] = in_1[3:0];
assign out_0 = mid[0];
assign out_1 = mid[1];

endmodule

///////////////////////////////////////
module inv_4b_v3 ( in_0, in_1, out );

input wire [3:0] in_0, in_1;
output wire [3:0] out[2];
wire [3:0] mid[2];

assign mid[0][3:0] = ~in_0[3:0];
assign mid[1][3:0] = in_1[3:0];
assign out = mid;

endmodule

////////////////////////////////////////

module packed2unpacked (b,a1, a0 );

input [3:0] a0;
input [3:0] a1;
output wire [3:0] b[2];

assign b[0]={a0[3],a0[2],a0[1],a0[0]};
assign b[1]={a1[3],a1[2],a1[1],a1[0]};

endmodule

//////////////////////////////////////////

module unpacked2packed (b,a1, a0 );

output wire [3:0] a0;
output wire [3:0] a1;
input wire [3:0] b[2];

assign a0=b[0];
assign a1=b[1];

endmodule

Hello. Andrew. I forgot to mention that all symbols are generated automatically by cadence after compiling the systemverilog codes.

Thank you.

I'm not sure how this worked - when I use cdsTextTo5x to import all the SystemVerilog, several of the modules failed, mostly because a pin defined like this (in inv_4b_v1):

input wire [3:0] in[2];
output wire [3:0] out[2];

can't really be represented in the database. On cdsTextTo5x it complains:

ERROR (TIVLOG-5013): Vector and Array are not supported simultaneously. Error occurred for netname
'in' at line number 16.

If you create in the systemVerilog text editor in Virtuoso, it seems to accept it, but the pins end up being called in<0:1> and out<0:1> which is not what's in inv_4b_v1. 

Fundamentally, pins in Virtuoso can be either simple scalar nets, or single-dimensional buses. Not this kind of multi-dimensional bus - they can't be represented in the OA database and so that means that the symbol and schematic can't support them either.

I suspect most of the rest of your issues are a consequence of this limitation.

Andrew