Verilog-ams generate-for loop with schematic reference

Similar Thread: https://community.cadence.com/cadence_technology_forums/f/mixed-signal-design/46762/verilogams-generate-for-loop-with-analog-behavioural-block

Hi all,

Firstly, thank you for reading.

I have a similar question, but this time, I reference a Virtuoso schematic instead of another AMS.

Following Andrew's suggestion, I add a dummy instance outside of the generate loop. Then I can see the cell I want to reference in Hierarchy Editor.

I set: View list: spectre schematic spice pspice verilog verilogams behavioral functional systemVerilog schematic veriloga vhdl vhdlams wreal

And for specify the cell bindings, I use the Table View in Hierarchy editor and force the view referenced by the generate loop to use the schematic view.

I make sure the REF_CELL only includes two views: schematic and symbol. So, I hope the AMS can auto-detect that there is only one view is able to use.

However, the schematic cannot be resolved automatically.

@Array_8x8<module>.genblk1[0].genblk1[0].U_CELL' of design unit 'REF_CELL ' is a leaf instance and is unresolved in cellview 'B_Array.Array_8x8:verilogams'. Ensure that the design unit is either pre-compiled or its corresponding text file is specified for compilation. Also, check the binding for this instance in Cadence Hierarchy Editor to confirm if it is set to externalHDL or addStopPoint or if nlAction is set to 'stop' for the specified instance.

How to specify the view to use for generating block? Is the only way manually unroll the loop? Any tools can help to do unrolling?

Env:

Spectre (R) Circuit Simulator
Version 20.1.0.382.isr12 64bit

Virtuoso IC6.1.8-64b.500.27

xrun(64): 20.03-s009

Thanks and best regards,

Simba