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Power supplies of standard cells

KhanAmir

Hi,

I have imported a verilog file in virtuoso. While importing I have specified the supplies as vdd and gnd but in the layout opened in the layout XL it is still showing the supplies as vdd! and gnd!. How can I overwrite these supply names to say VDD or VSS? I think there is some skill script is the to do this. Please help

Parents

  • What do you have in the Verilog code? Are there power/ground pins?

    These options are intended to be global power/ground nets, and to replace any 'b1 and 'b0 values in the netlist with these global nets. If you don't have that, you don't need to fill them in and you'll get conventional pins for the power/ground nets (assuming they are in the Verilog). 

    Put simply, it would help to see an example of the Verilog you are trying to import (you may be able to remove some of the content if it's sensitive to share).

    Andrew

  • in reply to Andrew Beckett

    Thanks for the response. Here is the code snippet

    module decoder (
    input i_en ,
    input [ 7:0] i_data,
    output reg [255:0] o_data
    );

    always@(*) begin
    if (~i_en) begin
    o_data <= {256{1'b0}};
    end else begin
    case (i_data)
    8'd0 : o_data <= {255'd0,1'b1};
    8'd1 : o_data <= {254'd0,1'b1,1'd0};
    8'd2 : o_data <= {253'd0,1'b1,2'd0};
    8'd3 : o_data <= {252'd0,1'b1,3'd0};
    8'd4 : o_data <= {251'd0,1'b1,4'd0};
    8'd5 : o_data <= {250'd0,1'b1,5'd0};
    8'd6 : o_data <= {249'd0,1'b1,6'd0};
    8'd7 : o_data <= {248'd0,1'b1,7'd0};
    8'd8 : o_data <= {247'd0,1'b1,8'd0};
    8'd9 : o_data <= {246'd0,1'b1,9'd0};
    8'd10 : o_data <= {245'd0,1'b1,10'd0};

    I am giving supply voltages while importing in virtuoso

  • in reply to KhanAmir

    I saw one file named "powerpins.il" in one of course which I had. I am giving this file to space based digital custom placer. I am attaching that file here. I don't know how to add the command to include power rails and overwrite the global signals.

    Fullscreen Power_routing_schemes_modified.txt Download 
    ;; ----------------------------------------
;; Scheme: pwr_ring
;; ----------------------------------------
(rteCreatePadRingScheme
	?name			'pwr_ring
	?allPinLayers		t
	?pinLayers		'("Metal1")
	?railPins		t
	?edgePins		nil
)
(rteCreateCoreRingScheme
	?name			'pwr_ring
	?ringAtCenter		nil
	?relativeTo		'insideIOPads
	?coreClearance		0.000000
	?padClearance		1.000000
	?inAreaClearance	0.000000
	?outAreaClearance	0.000000
	?areaXLo		0.000000
	?areaYLo		0.000000
	?areaXHi		0.000000
	?areaYHi		0.000000
	?horiLayer		"Metal1"
	?vertLayer		"Metal2"
	?latticeStyle		nil
	?netClearance		1.050000
	?netWidth		1.040000
)
(rteCreateBlockRingScheme
	?name			'pwr_ring
	?contour		nil
	?channel		nil
	?blockClearance		0.000000
	?horiLayer		"Metal1"
	?vertLayer		"Metal1"
	?latticeStyle		nil
	?netClearance		0.060000
	?netWidth		0.060000
)
(rteCreateStripesScheme
	?name			'pwr_ring
	?horiStripes		t
	?yStep			0.000000
	?horiLayers		nil
	?vertStripes		t
	?xStep			0.000000
	?vertLayers		nil
	?pinClearance		0.000000
	?netClearance		0.000000
	?netWidth		0.000000
	?minStripeLength	0.000000
	?offsetFrom		'designBoundary
	?leftOffset		0.000000
	?bottomOffset		0.000000
	?useCenterLine		nil
)
(rteCreateCellRowsScheme
	?name			'pwr_ring
	?routeLayers		'("Metal1")
	?endOfRow		nil
	?extendToNearest	t
)
(rteCreatePinToTrunkScheme
	?name			'pwr_ring
	?allPinLayers		t
	?pinLayers		'("Metal1")
	?useTrunkLayer		nil
	?trunkLayer		"Metal1"
	?minTrunkWidth		0.220000
	?minWireWidth		0.200000
	?maxWireWidth		0.250000
)
(rteCreateViasScheme
	?name			'pwr_ring
	?layerRange		t
	?minLayer		"Metal1"
	?maxLayer		"MetalF"
	?cutArrayRule		'rectangular
	?cutArrayRows		4
	?cutArrayColumns	4
)

;; ----------------------------------------
;; Scheme: dgnd_stripes
;; ----------------------------------------
(rteCreatePadRingScheme
	?name			'gnd_stripes
	?allPinLayers		t
	?pinLayers		'("Metal1")
	?railPins		t
	?edgePins		nil
)
(rteCreateCoreRingScheme
	?name			'gnd_stripes
	?ringAtCenter		nil
	?relativeTo		'insideIOPads
	?coreClearance		0.000000
	?padClearance		1.000000
	?inAreaClearance	0.000000
	?outAreaClearance	0.000000
	?areaXLo		0.000000
	?areaYLo		0.000000
	?areaXHi		0.000000
	?areaYHi		0.000000
	?horiLayer		"Metal1"
	?vertLayer		"Metal2"
	?latticeStyle		nil
	?netClearance		1.050000
	?netWidth		1.040000
)
(rteCreateBlockRingScheme
	?name			'gnd_stripes
	?contour		nil
	?channel		nil
	?blockClearance		0.000000
	?horiLayer		"Metal1"
	?vertLayer		"Metal1"
	?latticeStyle		nil
	?netClearance		0.060000
	?netWidth		0.060000
)
(rteCreateStripesScheme
	?name			'gnd_stripes
	?horiStripes		t
	?yStep			3.420000
	?horiLayers		'("Metal1")
	?vertStripes		nil
	?xStep			0.000000
	?vertLayers		nil
	?pinClearance		0.070000
	?netClearance		0.070000
	?netWidth		0.080000
	?minStripeLength	8.000000
	?offsetFrom		'designBoundary
	?leftOffset		0.000000
	?bottomOffset		0.190000
	?useCenterLine		nil
)
(rteCreateCellRowsScheme
	?name			'gnd_stripes
	?routeLayers		'("Metal1")
	?endOfRow		nil
	?extendToNearest	t
)
(rteCreatePinToTrunkScheme
	?name			'gnd_stripes
	?allPinLayers		t
	?pinLayers		'("Metal1")
	?useTrunkLayer		nil
	?trunkLayer		"Metal1"
	?minTrunkWidth		0.220000
	?minWireWidth		0.200000
	?maxWireWidth		0.250000
)
(rteCreateViasScheme
	?name			'gnd_stripes
	?layerRange		nil
	?minLayer		"Metal1"
	?maxLayer		"MetalF"
	?cutArrayRule		'rectangular
	?cutArrayRows		4
	?cutArrayColumns	4
)

;; ----------------------------------------
;; Scheme: vdd_stripes
;; ----------------------------------------
(rteCreatePadRingScheme
	?name			'vdd_stripes
	?allPinLayers		t
	?pinLayers		'("Metal1")
	?railPins		t
	?edgePins		nil
)
(rteCreateCoreRingScheme
	?name			'vdd_stripes
	?ringAtCenter		nil
	?relativeTo		'insideIOPads
	?coreClearance		0.000000
	?padClearance		1.000000
	?inAreaClearance	0.000000
	?outAreaClearance	0.000000
	?areaXLo		0.000000
	?areaYLo		0.000000
	?areaXHi		0.000000
	?areaYHi		0.000000
	?horiLayer		"Metal1"
	?vertLayer		"Metal2"
	?latticeStyle		nil
	?netClearance		1.050000
	?netWidth		1.040000
)
(rteCreateBlockRingScheme
	?name			'vdd_stripes
	?contour		nil
	?channel		nil
	?blockClearance		0.000000
	?horiLayer		"Metal1"
	?vertLayer		"Metal1"
	?latticeStyle		nil
	?netClearance		0.060000
	?netWidth		0.060000
)
(rteCreateStripesScheme
	?name			'vdd_stripes
	?horiStripes		t
	?yStep			1.710000
	?horiLayers		'("Metal1")
	?vertStripes		nil
	?xStep			0.000000
	?vertLayers		nil
	?pinClearance		0.070000
	?netClearance		0.070000
	?netWidth		0.080000
	?minStripeLength	8.000000
	?offsetFrom		'designBoundary
	?leftOffset		0.000000
	?bottomOffset		1.050000
	?useCenterLine		nil
)
(rteCreateCellRowsScheme
	?name			'vdd_stripes
	?routeLayers		'("Metal1")
	?endOfRow		nil
	?extendToNearest	t
)
(rteCreatePinToTrunkScheme
	?name			'vdd_stripes
	?allPinLayers		t
	?pinLayers		'("Metal1")
	?useTrunkLayer		nil
	?trunkLayer		"Metal1"
	?minTrunkWidth		0.220000
	?minWireWidth		0.220000
	?maxWireWidth		0.220000
)
(rteCreateViasScheme
	?name			'vdd_stripes
	?layerRange		nil
	?minLayer		"Metal1"
	?maxLayer		"MetalF"
	?cutArrayRule		'rectangular
	?cutArrayRows		4
	?cutArrayColumns	4
)

;; ----------------------------------------
;; Scheme: vdd_stripes
;; ----------------------------------------
(rteCreatePadRingScheme
	?name			'vdd_stripes
	?allPinLayers		t
	?pinLayers		'("Metal1")
	?railPins		t
	?edgePins		nil
)
;; ----------------------------------------
;; Scheme: Vias
;; ----------------------------------------
(rteCreatePadRingScheme
	?name			'Vias
	?allPinLayers		t
	?pinLayers		'("Metal1")
	?railPins		t
	?edgePins		nil
)
(rteCreateCoreRingScheme
	?name			'Vias
	?ringAtCenter		t
	?relativeTo		'outsideCore
	?coreClearance		0.000000
	?padClearance		0.000000
	?inAreaClearance	0.000000
	?outAreaClearance	0.000000
	?areaXLo		0.000000
	?areaYLo		0.000000
	?areaXHi		0.000000
	?areaYHi		0.000000
	?horiLayer		"Metal1"
	?vertLayer		"Metal2"
	?latticeStyle		nil
	?netClearance		0.060000
	?netWidth		0.20000
)
(rteCreateBlockRingScheme
	?name			'Vias
	?contour		nil
	?channel		nil
	?blockClearance		0.000000
	?horiLayer		"Metal1"
	?vertLayer		"Metal1"
	?latticeStyle		nil
	?netClearance		0.060000
	?netWidth		0.060000
)
(rteCreateStripesScheme
	?name			'Vias
	?horiStripes		t
	?yStep			0.000000
	?horiLayers		nil
	?vertStripes		t
	?xStep			0.000000
	?vertLayers		nil
	?pinClearance		0.000000
	?netClearance		0.000000
	?netWidth		0.000000
	?minStripeLength	0.000000
	?offsetFrom		'designBoundary
	?leftOffset		0.000000
	?bottomOffset		0.000000
	?useCenterLine		nil
)
(rteCreateCellRowsScheme
	?name			'Vias
	?routeLayers		'("Metal1")
	?endOfRow		nil
	?extendToNearest	t
)
(rteCreatePinToTrunkScheme
	?name			'Vias
	?allPinLayers		t
	?pinLayers		'("Metal1")
	?useTrunkLayer		nil
	?trunkLayer		"Metal1"
	?minTrunkWidth		0.200000
	?minWireWidth		0.200000
	?maxWireWidth		0.220000
)
(rteCreateViasScheme
	?name			'Vias
	?layerRange		t
	?minLayer		"Metal1"
	?maxLayer		"MetalF"
	?cutArrayRule		'rectangular
	?cutArrayRows		1
	?cutArrayColumns	1
)

  • in reply to KhanAmir

    You might want to take a look at VerilogIn maps VDD, GND, tie Low 1'b0 and tie High 1'b1 nets to VDD! and GND! which are Global power and ground . However, in this case, your Verilog code is behavioural, so I'm not sure this is going to be terribly relevant since the behavioural code can't be changed to a schematic.

    Andrew

  • in reply to KhanAmir
    KhanAmir said:
    saw one file named "powerpins.il" in one of course which I had.

    This appears to have nothing to do with the thread here - did you post in the wrong place? These functions are related to layout routing.

    Andrew

Reply Children
  • in reply to Andrew Beckett

    The thing is I have synthesized the code using genus. Default supplies for standard cells are vdd! and gnd!. I imported the synthesized code to virtuoso and while importing the design global power options I gave vdd and dgnd. I am using Space based digital custom placer. Now, when I am seeing the layout of individual cells they are showing global supplies only not the one I gave while importing. Sorry, if it is at wrong forum. 

  • in reply to KhanAmir

    But the code you mentioned above is not the synthesised code - that's behavioural code.

    I'm not sure what the "Space-based digital custom placer" is. We have a space-based router, but not a space-based placer.

    Perhaps you should contact customer support, as otherwise we may be just talking at cross purposes here.

    Andrew

  • in reply to Andrew Beckett

    Hi Andrew, you are right it is router. Sorry, initially I sent you only behavioral code which is not required. Following is the synthesized code. In this code, there is no specification of power supplies anywhere. As I mentioned previously that default power and ground nets of standard cells are vdd! and gnd!.

    module decoder(i_en, i_data, o_data);
    input i_en;
    input [7:0] i_data;
    output [255:0] o_data;
    wire i_en;
    wire [7:0] i_data;
    wire [255:0] o_data;
    wire n_0, n_3, n_5, n_6, n_7, n_8, n_9, n_10;
    wire n_12, n_13, n_14, n_15, n_16, n_44, n_70, n_99;
    wire n_102, n_112, n_113, n_116, n_119, n_126, n_128, n_130;
    wire n_160, n_162, n_166, n_174, n_177, n_180, n_194, n_200;
    wire n_205, n_210, n_217, n_223, n_226, n_231, n_235, n_238;
    wire n_240, n_257, n_259, n_261, n_263, n_269, n_272, n_274;
    wire n_277, n_289, n_294, n_296, n_298, n_300, n_302, n_304;
    wire n_310, n_312, n_314, n_316, n_319, n_337, n_344, n_351;
    wire n_358, n_365, n_372, n_379, n_386, n_488, n_493, n_498;
    wire n_503, n_508, n_513, n_518, n_523, n_524, n_525, n_526;
    AND2_X6 g5993__8780(.A1 (n_316), .A2 (n_277), .Q (o_data[153]));
    AND2_X6 g5865__4296(.A1 (n_319), .A2 (n_314), .Q (o_data[190]));
    AND2_X6 g5867__3772(.A1 (n_319), .A2 (n_312), .Q (o_data[189]));
    AND2_X6 g5933__1474(.A1 (n_319), .A2 (n_310), .Q (o_data[188]));
    AND2_X6 g5854__4547(.A1 (n_316), .A2 (n_296), .Q (o_data[187]));
    AND2_X6 g5908__9682(.A1 (n_316), .A2 (n_314), .Q (o_data[186]));
    AND2_X6 g5915__2683(.A1 (n_316), .A2 (n_312), .Q (o_data[185]));

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