read a file .csv and .mat with verilog-A

Dear Hagar Hendy,

Hagar Hendy said:

I want to write code with Verilog A that could read weights with extension (.mat) that generated from tensor flow, to upload that as file written by Verilog A, as well as to read a file with .csv file that can read inputs or the dataset. How to do that?

The verilog-A reference manual covers commands to provide file I/O. There is a note where I included an example of some verilog-A code to read data from a comma-separated variable file in the Forum post at URL:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/52283/datapoints-memory-array/1384990#1384990

There is a link in the post that details the code and illustrates its operation.  The link is a Dropbox link ,and I can no longer include the URL as text as my response will be flagged as spam. The note is at URL:

and can be accessed from the Forum post I referred you to. The verilog-A code is also attached to that post.

I hope I understood your need and this is somewhat helpful!

Shawn

I have more than one question regarding the code as i try to run it, but before that i want to understand the code. 

@initial step , there are 10 count ( from count0 to count 9 ) and then after scanf there another ( count0 to count 9 ) and that also repeated , can you clarify that is that to represent the delay the 30 ns sec that mentioned ? 

Dear Hagar Hendy,

Hagar Hendy said:

@initial step , there are 10 count ( from count0 to count 9 ) and then after scanf there another ( count0 to count 9 ) and that also repeated , can you clarify that is that to represent the delay the 30 ns sec that mentioned ? 

The two snippets of code that appear as repeated sections are each instantiated at the onset of the simulation defined by the statement:

@(initial_step) begin

and when the input clock crosses the value of vthreshold defined by the statement:

@ cross(V(clkin)-vthreshold, +1) begin

In this verilog-A code, I included the variable tdelay and set it to 0. Therefore, the original Forum poster could set the delay = 30n  in order to include a 30 ns delay between the input clock edge to the output clock. In the example output shown on page 7 and highlighted in Figure 1, there is no delay between the input clock rising edge and output data signals.

Shawn

Figure 1

i am new to Verilog-A, could you please tell me again the reason for the reptations?

@(initial_step) begin

and when the input clock crosses the value of vthreshold defined by the statement:

@ cross(V(clkin)-vthreshold, +1) begin

 i think it will be cleared if i could run the code, i wrote the text file for the inputs  (.txt), but when i run , there is an error highlighted at 

@ cross(V(clkin)-vthreshold, +1) begin, so i don't know what is the problem 

Also regarding the clk_in , how you represent its value in the code ? is that V0?,

Dear Hagar Hendy,

Hagar Hendy said:

i am new to Verilog-A, could you please tell me again the reason for the reptations?

@(initial_step) begin

and when the input clock crosses the value of vthreshold defined by the statement:

@ cross(V(clkin)-vthreshold, +1) begin

I think you should consider spending a little of your time reviewing a reference on verilog-A or as a minimum some samples in the Cadence behavioral library supplied with your installation. There is also a Cadence reference manual in your installation. I'm happy to help, but it might save you some time.

But, just to try to explain, the initial_step is instantiated at the start of your simulation and does not require any clock to cross a threshold for it to be executed. The second @ cross set of commands will be executed only when ckin crosses the threshold vthreshold with a positive slope.

Hagar Hendy said:

 i think it will be cleared if i could run the code, i wrote the text file for the inputs  (.txt), but when i run , there is an error highlighted at 

@ cross(V(clkin)-vthreshold, +1) begin, so i don't know what is the problem 

I am afraid you have not provided me enough information to give a more concrete answer, However, did you convert the inputs.txt file to a comma-separated variable file as shown on page 6 of the note I referred you? There is a simple shell script that performs the conversion. The verilog-A code I outlined is designed to read a comma-separated variable file. The inputs.txt file has no comma delimiters in it and the code is expecting 10 per line.

Hagar Hendy said:

Also regarding the clk_in , how you represent its value in the code ? is that V0?,

The input pin clkin of the symbol for the block is connected to the pulse source in the schematic. Note that the verilog-A function has an input whose name is the input pin of the symbol.

Shawn

thanks, here is another question ,  why you define (count0 to count 9) and not start (v0_int:v9_int)  as it define as real , what is the usage of count as in transition you use (v0_int:v9_int)

Dear Hagar Hendy,

Hagar Hendy said:

why you define (count0 to count 9) and not start (v0_int:v9_int)  as it define as real , what is the usage of count as in transition you use (v0_int:v9_int)

After reading the input file data as floating point values, since the values are intended as binary inputs with value 1 or 0, re-assigning the real values of val0-val9 to the integer values count0-count9 performs the type conversion to integer. Hence, if the input data was read as 1.000001 as val0 it will be converted to 1 as count0. The real variables v0_int to v9_int receive the integer values for use in the output transition statements.

Please refer to chapter 4 of the Cadence manual at URL:

https://support.cadence.com/apex/techpubDocViewerPage?path=veriaref/veriaref21.1/veriarefTOC.html

Shawn

thanks, but when i press on the link that you mentioned, this screen comes and i am not able to do anything with that page 

also, i run the code, but this is the output is shown as below they are all zeros, so this is mean that it read text file  wrong, what i did is that i opened a text file and i put random number with commas and i rename it as .csv ,is that works?  or i have to use the code that used for conversion ?

Dear Hagar Hendy,

Hagar Hendy said:

but when i press on the link that you mentioned, this screen comes and i am not able to do anything with that page

You need to contact whomever administers your Cadence tools and request the information to conplete this form.I highly suggest you follow throgh and set up an account as there is a wealth of information available that I think will be both interesting and helpful to you. For example, the URL I provided is a link to the current the verilog-A reference manual.

Shawn

Dear Hagar Hendy,

Hagar Hendy said:

but when i press on the link that you mentioned, this screen comes and i am not able to do anything with that page

You need to contact whomever administers your Cadence tools and request the information to conplete this form.I highly suggest you follow throgh and set up an account as there is a wealth of information available that I think will be both interesting and helpful to you. For example, the URL I provided is a link to the current the verilog-A reference manual.

Shawn

Dear Hagar Hendy,

Hagar Hendy said:

also, i run the code, but this is the output is shown as below they are all zeros, so this is mean that it read text file  wrong, what i did is that i opened a text file and i put random number with commas and i rename it as .csv ,is that works? 

You really have not provided me with enough information to give you a specific answer. For example, what random numbers (posiitive/negative/integers/fractional)? and how many per line? Did you save the file as a UNIX file? Did you include the filename as the verilog-A input filename?

If you are trying to duplicate the result, perhaps you should use the example file I used in the note and follow the exact instructions I used.

Shawn

Dear Hagar Hendy,

In addition to the useful suggestions from Shawn, you can also access the Verilog-A documentation entirely within your software - use <SPECTREinstDir>/bin/cdnshelp - it is all shipped with the software. So you may not even need to connect to the support site (although resolving that would be a good idea anyway).

Regards,

Andrew