PLL PSS simulation in spectre

Dear RaghavendraN,

RaghavendraN said:

I am wondering how to run PSS for PLL ( PLL contains VCO also ) ? Does cadence supports this kind of spectre simulation? If so, do you have any documentation on how to do that?

I am not sure what level you are interested in performing your simulations and hence cannot provide a definite answer. However, I will outline some personal comments for the two most common situations.

Case 1: Transistor level

If you are considering running a transistor level simulation, I might suggest you review some comments I made recently in response to a recent similar question at the Forum post:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/55593/observing-pll-phase-noise-with-hbnoise/1387948#1387948

This response includes references to a few Cadence documents on the subject.

Case 2: Behavioral level

Simulations of the response of a PLL at the behavioral level are feasible using conventional transient analyses and transient noise analyses (assuming your behavioral models accurately represent salient noise sources. Verilog-A models for the loop components - or most of them - make the simulation resources reasonable.

There are many good resources publicly available for writing accurate and robust verilog-A models for the various loop components.

Shawn

Dear RaghavendraN,

RaghavendraN said:

I am wondering how to run PSS for PLL ( PLL contains VCO also ) ? Does cadence supports this kind of spectre simulation? If so, do you have any documentation on how to do that?

I am not sure what level you are interested in performing your simulations and hence cannot provide a definite answer. However, I will outline some personal comments for the two most common situations.

Case 1: Transistor level

If you are considering running a transistor level simulation, I might suggest you review some comments I made recently in response to a recent similar question at the Forum post:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/55593/observing-pll-phase-noise-with-hbnoise/1387948#1387948

This response includes references to a few Cadence documents on the subject.

Case 2: Behavioral level

Simulations of the response of a PLL at the behavioral level are feasible using conventional transient analyses and transient noise analyses (assuming your behavioral models accurately represent salient noise sources. Verilog-A models for the loop components - or most of them - make the simulation resources reasonable.

There are many good resources publicly available for writing accurate and robust verilog-A models for the various loop components.

Shawn