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write a verilog-A for inverter

i want to define vdd correctly, there is an error that i am using wrong data type. i defined it as electrical signal and at the same time the value of the vdd is 1.2 V so it constant, so how can i do that ?

here is the code that i used

`include "constants.vams"
`include "disciplines.vams"

module inverter_1 (out,in);

output out;
input in;
electrical out, in;
integer d_out,vdd;

analog begin
vdd= 1;
@(cross(V(in) - 0.5*V(vdd)));
if (V(in)>0.5*V(vdd))
d_out =0;
else
d_out =1 ;
V(out) <+ transition(d_out,0,10ns)*V(vdd);
end
endmodule

Andrew Beckett over 2 years ago

You have vdd as a variable (which is set to 1, not 1.2) but yet you are referring to it as the voltage of a node called vdd with electrical discipline - but you have not defined it as a electrical node.

If you change all the V(vdd) to just vdd, and change the 10ns to 10n, the code will work.

Either that, or have vdd as one of the signals passed into the inverter, and remove the real vdd and vdd=1 from the code.

Andrew
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Hagar Hendy over 2 years ago in reply to Andrew Beckett

thank you so much, it works
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