SystemVerilog nettype and resolution function in Virtuoso schematic hierarchy

Dear HoWei,

2) When using the predefines "cds_rnm_package" reslution functions and I want to exchange my systemVerilog models with a design-partner who is using another tool (Synopsys, Mentor) how can they acces the "cds_rnm_pkg" ?

cds_rnm_package is a Cadence sv replacement to the existing wrealAMS nettypes that you mentioned above(wrealsum, wrealavg, wrealmax etc.) the package comes precompiled with your xcelium installation. If you are using different vendors I would recommend that you create a new cds_rnm_pkg.sv file which contains all your resolution functions you need and nettypes. This way you stay consistent across different vendors.

 https://support.cadence.com/apex/techpubDocViewerPage?xmlName=sysverilog.xml&title=SystemVerilog%20Reference%20--%20Data%20Types%20-%20Resolution%20Functions&hash=DataTypes-ResolutionFunctions&c_version=22.09&path=sysverilog/sysverilog22.09/Data_Types.html#DataTypes-ResolutionFunctions

1) If I create the hierarchy in schematics (Virtuoso) and not in a systemVerilog module, how can I specify the nettype of the interconnections ?

The answer to this question is slightly more complicated.

1) First you have to import all the packages you are using for your new nettypes. There's multiple ways to do this. In newer versions of virtuoso we have added a tool to do this for you. Or you can precompile all your packages into directories and point to them in you cds.lib file.

2) As you are familiar to simulate you have to generate a netlist first, you have an option between UNL or SystemVerilog netlister. For Digital Mixed Signal Simulations you will need our DMS license. You can either nettlist the design with nettype propogation enabled in the SV netlister(explicit netlisting), you can have your nets netlisted implicitly, or as interconnects. Xcelium DMS simulator has the advantage of coercion that existed in verilogAMS where implicit wire nets were coerced to the nettype they were connected to . 

Thanks for the detailed answer and the link.

2) After a discussion with our partner, it should work when I define the nettypes in my SV code (e.g. input wrealsum myinput; ) and include "import cds_rnm_pkg::*; ).

The only thing the partner need to do is to replace "cds_rnm_pkg::*" with his tool-vendors predefined package (which uses the same predefined nettypes) and run the code. To keep the code flexible among different tools, a condition might be included to either import the "cds_rnm_pkg" ot the other tool-vendors package. This is something we need to try now.

1.1) To include the required packages (dmsLib, etc.) I am using the "CIW-->Tools-->AMS-->HDL Package Setup"  feature, since it allows to configure the HDL setup not only for simulations, but also for compilation (Check&Save) from within the text-editor.

Is this the tool you are referring to ?

1.2) I think Virtuoso 6.1.8 already uses AMS-UNL per default (at least it is the only option shown in the netlister settings) since I start it from a maestro-view. But regarding explicit, implicit or interconnect netlisting, I have no idea and a quick search on google and Cadence help did not help much.  

Do you have a link or can you give a brief explanation on the differences ?

What I am doing right now is to define the ports of a module like this:

import cds_rnm_pkg::*;

module mymodule(

   input wrealmax myinput;

   output wrealsum myoutput;

)

And I need to ensure that the ports of the connected modules do have the same nettype defined.  Is this explicit netlisting ?

2) After a discussion with our partner, it should work when I define the nettypes in my SV code (e.g. input wrealsum myinput; ) and include "import cds_rnm_pkg::*; ).

The only thing the partner need to do is to replace "cds_rnm_pkg::*" with his tool-vendors predefined package (which uses the same predefined nettypes) and run the code. To keep the code flexible among different tools, a condition might be included to either import the "cds_rnm_pkg" ot the other tool-vendors package. This is something we need to try now.

Yes you are correct about this. it's best that you do all this in one share package and keep it out of your code. 

1.1) To include the required packages (dmsLib, etc.) I am using the "CIW-->Tools-->AMS-->HDL Package Setup"  feature, since it allows to configure the HDL setup not only for simulations, but also for compilation (Check&Save) from within the text-editor.

Is this the tool you are referring to ? YES

if you dont want to use that one other option is to point to the precompiled packaged in your cds.lib

DEFINE dmsLib $AMSHOME/tools/affirma_ams/etc/dms/dmsLib

If you go into the dmsLib directory you will find precompiled cds rnm packages, ofcourse you have to do that with every package you want to import. 

.2) I think Virtuoso 6.1.8 already uses AMS-UNL per default (at least it is the only option shown in the netlister settings) since I start it from a maestro-view. But regarding explicit, implicit or interconnect netlisting, I have no idea and a quick search on google and Cadence help did not help much.  

Do you have a link or can you give a brief explanation on the differences ?

You are correct when you running your testcases in virtuoso, the final netlist you generate will use UNL. I was referring to our systemVerilog netlisting tool, this way you can share the netlist across different vendors. Now this is meant for batch mode simulations but setup is done through the virtuoso hierarchy editor and config views.  

Use the link below to see how you can use the sv netlisting gui and set up netlist directives

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009xy8WEAQ&pageName=ArticleContent

Use the link below to do command line netlisting this is more involved and I can provide you later with examples if you need to. If you need help and we have an NDA signed I can do a teams meeting with you. 

https://support.cadence.com/apex/techpubDocViewerPage?xmlName=vsvn.xml&title=Virtuoso%20SystemVerilog%20Netlister%20User%20Guide%20--%20runsv%20-%20runsv&hash=pgfId-1123751&c_version=ICADVM20.1&path=vsvn/vsvnICADVM20.1/appOptions_re_runsv.html#pgfId-1123751

For UNL you can refer to 

https://support.cadence.com/apex/techpubDocViewerPage?xmlName=explorer.xml&title=Virtuoso%20ADE%20Explorer%20User%20Guide%20--%20Working%20with%20AMS%20Simulator%20-%20runams%20Command%20Options&hash=pgfId-1056950&c_version=ICADVM20.1&path=Explorer/ExplorerICADVM20.1/chap15.html#pgfId-1056950

Hi,

would the SV netlisting (using HED/config hierarchy) in batch mode allow to speed up the compilation/elaboration/simulation process ?

If yes, I would be interested to have a meeting and discuss those topics, as we do have a support contract with Cadence.

But if the batch mode will not change the simulation time, I do not see a reason to change the current flow.

The current status for the AMS simulation in virtuoso is, that a simple minimal module wil ltake more than 6 minutes !

After 1min40sec the xrun-logfile opens and starts comiplation.

After 3:40 the compilation is finished and elaboration starts.

After 5:30 the elaboration is finished and simulation starts with reading in all files.

After 6:50 the simulation is finished, for which the time-domain simulation itself took only some seconds.

This means I cannot do more than 10 simulations per hour - this is really annoying if you have to debug code.

The xrun.log file reports the following times:

xmvlog: CPU Usage - 0.0s system + 0.1s user = 0.2s total (0.2s, 77.6% cpu)

xmelab: CPU Usage - 0.2s system + 0.3s user = 0.5s total (0.7s, 71.2% cpu)

Total License Acquisition Time : 24.1 s.
      xmsim : License Acquisition Time -- 18.4 s.
      spectre: License Acquisition Time -- 5.69 s.

xmsim: CPU Usage - 4.9s system + 37.3s user = 42.1s total (80.4s, 52.4% cpu)

What is Cadence doing for the rest of the time ?

If there is any way to speed-up the simulations, please lets have  a meeting !

EDIT: I found that the long time for simulation is caused by modelfiles from PDK and IPs (standardcells) which are somehow included in the simulation, even if not a single component is used from those libs.   Excluding/disabling the modelfiles was improving the speed adn it takes only 1:40min until the simulation is finished.  Still strange to understand what the tool is doing when including modefiles in AMS simulations.

EDIT: I found that the long time for simulation is caused by modelfiles from PDK and IPs (standardcells) which are somehow included in the simulation, even if not a single component is used from those libs.   Excluding/disabling the modelfiles was improving the speed adn it takes only 1:40min until the simulation is finished.  Still strange to understand what the tool is doing when including modefiles in AMS simulations.

This has to do with your AMS setup file both analog models and your xrun args file. 

We can definitely try a simple minimal module as you said and see if there's any improvement, but since in both cases the simulator is Xcelium I don't think we will see improvements. But in general systemVerilog netlist is my preferred way of running DMS simulation. You have to see what makes sense for your project. If the models are being shared it's best to keep them outside of library manager and import them using cdsTextTo5x using symbolic links instead of hard copies. Afterwards you can edit your models through library manager or you can edit them outside of virtuoso it gives you some flexibility.