SysVerilog bidirectional port with wreal nettype from cds_rnm_pkg

Hi,

I was following this tutorial video https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009bfBiEAI&pageName=ArticleContent and created my own design. It uses the Cadence internal "$cged()" function to assign internal variables with the resolved net value of the declared nettype.

It will model 2 transmission gates, where each gate has 2 ports (A,B). The first gate has the nettype "wrealsum", whereas the second gate has the nettype "wrealmax".  This shall lead to different values on the nets, when the transimmion gate is enabled and driven with multiple drives (which is not the case in this example - here only 1 driver is connected):

import cds_rnm_pkg::*; //from dmsLib

`define resTyp1 wrealsum
`define resTyp2 wrealmax

module tb_wreal_TXRXdmy (
inout `resTyp1 InOut1A,
inout `resTyp1 InOut1B,
inout `resTyp2 InOut2A,
inout `resTyp2 InOut2B,
input logic control
);

//internal nets to store the external resolved value
`resTyp1 io1A;
`resTyp1 io1B;
`resTyp2 io2A;
`resTyp2 io2B;

initial begin
$cged(InOut1A, io1A); //$cged is required to store
$cged(InOut1B, io1B); //the resolved net value
$cged(InOut2A, io2A); //of the outside driving
$cged(InOut2B, io2B); //resolution function
end

//assign the internal signal to the other port
assign InOut1A = (control==1'b1) ? `wrealZState : io1B;
assign InOut1B = (control==1'b1) ? `wrealZState : io1A;
assign InOut2A = (control==1'b1) ? `wrealZState : io2B;
assign InOut2B = (control==1'b1) ? `wrealZState : io2A;

endmodule

The "control" is stimulated with a clock signal (20ns periode) and the input signals are applied to "InOutA1= 4.0" and "InOutA2=3.0". Both output signals "InOutB1" and "InOutB2" are open (not connected).

What I am expecting to see at the outputs is values toogling between the input values "4.0/3.0" and "Z".  But this is not the case.

Instead the output values at "InOutB1" and "InOutB2" are constantly showing the input signals "4.0/3.0".  

Why is that - any idea ?