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Differences between Verilog, Verilog-A, Verilog-AMS and SystemVerilog

HoWei

Hi,

still I am struggling to understand the full differences between Verilog, Verilog-A, Verilog-AMS and SystemVerilog - because I see very often both (Verilog-AMS and SystemVerilog) considered as the same thing. It even happended when asking Cadence support for an SystemVerilog problem and I received a Verilog-AMS solution.  Or when searching for SV real-number-modelling, you end up getting Verilog-AMS result and proposals.  I am missing a clear distinction.

In this post want to sort-out the difference between the different languages. Here is what i understood so far:

Verilog:

- descibes pure logic behaviour (states: 0, 1, X, Z)

- simulation requires a pure logic simulator (e.g. Xcelium)

- can be used for digital synthesis 

- is a IEEE standard

Verilog-A:

- descibes analog circuit behaviour - modelling with voltages and currents

- simulated requires an analog simulator (e.g. Spectre)

- cannot be used for digital synthesis

- not an IEEE standard -  it belongs to company Accellera

Verilog-AMS:

- a combination of  Verilog and Verilog-A - allows logic and real-number-modelling (e.g. wreal built-in resolution functions)

- simulation requires both digital and analog simulators (e.g. Xcelium and Spectre) in vendor specific tool-environment (Virtuoso-AMS)

- cannot be used for digital synthesis

- not an IEEE standard - it belongs to company Accellera

SystemVerilog:

- an extension to Verilog - allows logic and real-number-modelling (e.g. no built-in - but option for customized -  resolution functions)

- simulation requires digital simulator (e.g. Xcelium)

- can be used for digital synthesis

- is an IEEE standard

Here are some open questions:

1. Requires Verilog-AMS code an analog simulator, or can Verilog-AMS code also be simulated in a pure logic simulator (e.g. Xcelium) ?

2. When I want to write portable models (behavioral models that can be reused in other simulators from Mentor, Synopsys, etc.), can I do this for both Verilog-AMS and SystemVerilog ?

3. When I want to write portable models for a pure digital simulator with real-number-modelling, I assume SystemVerilog would be the correct choice ?

What really puzzles me is,  that often SystemVerilog and Verilog-AMS will be considered the same thing and that Verilog-AMS code snippets are provided as solution for SystemVerilog problems.

Parents

  • 1. Verilog-AMS code can be run on a logic simulator if the code is limited to just the digital domain and no "analog" blocks or "electrical" signals. At that point, it may be called Verilog-AMS, but it is really just the Verilog subset.

    2. Theoretically, if you stick to the LRM, the models should run on other simulators. However, not all vendors have implemented all aspects of the LRM (especially Verilog-AMS).

    3. SystemVerilog has the most comprehensive set of constructs for RNM. Verilog-AMS does have 'wreal' construct but it is not supported equally by all vendors and does not provide as much capability as SystemVerilog or VHDL.

    SystemVerilog and Verilog-AMS are not considered the same thing. You probably had a problem that could be solved with either VAMS code or SV code, but they would be two different solutions. Xcelium can run Verilog, SystemVerilog, Verilog-AMS, VHDL, and VHDL-AMS, but it doesn't mean those are all the same thing. They are different languages that are all supported by a single simulator.

Reply

  • 1. Verilog-AMS code can be run on a logic simulator if the code is limited to just the digital domain and no "analog" blocks or "electrical" signals. At that point, it may be called Verilog-AMS, but it is really just the Verilog subset.

    2. Theoretically, if you stick to the LRM, the models should run on other simulators. However, not all vendors have implemented all aspects of the LRM (especially Verilog-AMS).

    3. SystemVerilog has the most comprehensive set of constructs for RNM. Verilog-AMS does have 'wreal' construct but it is not supported equally by all vendors and does not provide as much capability as SystemVerilog or VHDL.

    SystemVerilog and Verilog-AMS are not considered the same thing. You probably had a problem that could be solved with either VAMS code or SV code, but they would be two different solutions. Xcelium can run Verilog, SystemVerilog, Verilog-AMS, VHDL, and VHDL-AMS, but it doesn't mean those are all the same thing. They are different languages that are all supported by a single simulator.

Children
  • in reply to tpylant

    Thanks, that confirms my understanding of the differences between those languages.

    We want to create real-number-models for our analog blocks (ADC, LDO, Amplifiers, T-Gates) - including bidirectional ports (signal-flows), which can be shared with our design partner.

    We are using Cadence AMS (Spectre, Xcelium) and our design partner is using Synopsys VCS.

    We decided for SystemVerilog, but especially with bidirectional ports, we do see severe issues between the tools and do have trouble to write code which can run in both tools.  At the moment we are using 'ifdef - conditions to distinguish between tools and have 2 seperate codes to resolve bidirectional ports. This is very inconvenient, since we cannot test the VCS code part, when writing the models.

    1. Have you have ever had a similar situation ?

    2. From your experience, which modelling language would be the most convenient to achieve this ?

    3. Do you think custom SV resolution functions would help here, which would be part of the modelling and can be used from both tools ?

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