expecting a valid compiler directive error in vams that is not in systemVerilog

I have a single test bench that has two views:  one is all digital using sv models for analog blocks, and the other has analog blocks along with digital content.

I was not able to compare wreal nodes in hierarchy because the simulator was adding interface elements.  I was able to find Unified VerilogAMS monitor to probe electrical/real/wreal/logic signals in a test bench (cadence.com) from the support website.  This fixed my issue for my all digital test bench.

However, when I try the same code in the mixed signal bench, it fails, saying "expecting a valid compiler directive" for the `define create_monitor macro.  The top level stimulus for that bench is a verilog.vams file.  The all digital stimulus is a verilog.sv file.

This is easily reproducible using the example that is located in the link above.  That example runs for me (changing the "run" file to use xrun instead of irun).  But, rename the file "top.sv" to "top.vams", and change the "run" file to use top.vams, and you get the error:

`create_monitor(I_monitor_1,top.I1.net1,,,1)
 |
xmvlog: *E,EXPCPD (top.vams,10|43): expecting a valid compiler directive [16(IEEE)].
(`define macro: create_monitor [top.vams line 1], file: top.vams line 10)
`create_monitor(I_monitor_2,top.I2.net2,,,1)
 |
xmvlog: *E,EXPCPD (top.vams,11|43): expecting a valid compiler directive [16(IEEE)].
(`define macro: create_monitor [top.vams line 1], file: top.vams line 11)
`create_monitor(I_monitor_3,top.I3.net3,,,1)
 |
xmvlog: *E,EXPCPD (top.vams,12|43): expecting a valid compiler directive [16(IEEE)].
(`define macro: create_monitor [top.vams line 1], file: top.vams line 12)
`create_monitor(I_monitor_4,top.I4.net4,,,1)
 |
xmvlog: *E,EXPCPD (top.vams,13|43): expecting a valid compiler directive [16(IEEE)].
(`define macro: create_monitor [top.vams line 1], file: top.vams line 13)

Since vams should be able to handle `define macros, what could be going on?