VAA: Vector and Array are not supported simultaneously

I am trying to do a mixed signal siumulation of my design in virtuoso using the AMS simulator. I have a system verilog model with the following code,

//systemVerilog HDL for "bhu_MSD", "sil_gpo" "systemVerilog"

module sil_gpo #(
parameter N = 32'd1
) (
input logic clk,
input logic rst_n,
output logic [31:0] gpio_o [N]
);


Though I am able to compile such a definition in ncsim, I am not able to do the same in my virtuoso system verilog compiler. When I try to comiple I get the following error message,

SystemVerilog *E, VAA: Vector and Array are not supported simultaneously.
Error occurred for netname 'gpio_o' at line number 43.

Is there anything that I could do to make this compilable. If not I would have to change several instances and several lines of code in my orginal digital design.