Stats

  • Locked Locked
  • Replies 2
  • Subscribers 63
  • Views 6664
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

cds_global varible errors in config mode

Binhngo1210

Hi all, 

i am testing a co-simulation of spectre netlist and verilogA code as the capture 1 below so i create config file for this run. 

However when running with ADE explorer, error like the capture 2 happened with cds_global varibles. ( this varibles are in vpulse source setting) 

when i run directly from schematic without using config file, netlist like capture 3 and simulation works out as the normal. 

How can i resolve this problem for config file use? 

Thanks for any help. 

TM

cap.1

cap.2

cap.3

Parents

  • That is very odd indeed. It appears from the netlist that you are using spectre as the simulator; if so, cds_globals should never appear in the netlist. That comes from when the simulator is "ams" - but then that would be in a Verilog-AMS netlist (which would be fine). If you'd been using "ams" as the simulator, you can't netlist without a config - so something does not add up here. If spectre is the simulator, there's no "co-simulation" going on here (because spectre itself handles Verilog-A).

    Which IC sub-version are you using? I see you're using a Spectre version from 5-6 years ago, but even so I can't find any reports of this issue and don't recall ever having seen it either.

    I would strongly encourage you to contact customer support (submit a case after logging in). This is so unusual, that we really will need to see it, I think.

    Regards,

    Andrew

Reply

  • That is very odd indeed. It appears from the netlist that you are using spectre as the simulator; if so, cds_globals should never appear in the netlist. That comes from when the simulator is "ams" - but then that would be in a Verilog-AMS netlist (which would be fine). If you'd been using "ams" as the simulator, you can't netlist without a config - so something does not add up here. If spectre is the simulator, there's no "co-simulation" going on here (because spectre itself handles Verilog-A).

    Which IC sub-version are you using? I see you're using a Spectre version from 5-6 years ago, but even so I can't find any reports of this issue and don't recall ever having seen it either.

    I would strongly encourage you to contact customer support (submit a case after logging in). This is so unusual, that we really will need to see it, I think.

    Regards,

    Andrew

Children
  • in reply to Andrew Beckett

    Thanks for your quick response, 

    however in this case i want to test with ams simulator. I will add another verilog inverter to make sense the purpose. However, in case of ams simulator, the cds_global comes up in netlist and my simulation was stuck there. How can i resolve it ? 

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.