• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Mixed-Signal Design
  3. Measure a branch current in Verilog AMS (Probe Command)

Stats

  • Locked Locked
  • Replies 0
  • Subscribers 64
  • Views 6468
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Measure a branch current in Verilog AMS (Probe Command)

Devin Atkin
Devin Atkin over 2 years ago

My current setup for the model I'm writing is very rudimentary, but I want to simulate it with very idealized behavior before I start accounting for anything. 

Currently I'm just accounting for the current through the ports OUT_N, and OUT_P. When I simulate it I can see the current flow; however, I want to see if over time not, just at the point the simulation stops. I think my issue is with my probe command which I grabbed awhile back with another module and have been slowly adjusting as needed. 

probe -create -emptyok -all -shm -database waves {OUT_N}
This was what I had initially hopped should give me the current flowing in through the port as I've set it to 3.3V which I can see fine; however, I cannot see the current flow into the port of the Verilog AMS module. I've tried manually defining branches, I've tried to use the inhconn_signal to try and get the flow with that. I feel I'm lacking something fundamental. 
Here's my testbench code
`include "disciplines.vams"
`include "constants.vams"

module PIXEL_TB();

electrical SINE_IN, OUT_P, OUT_N;
electrical vdd, gnd;
ground gnd;


PIXEL DUT (.SINE_IN(SINE_IN),.I_OUTP(OUT_P),.I_OUTN(OUT_N),.gnd(gnd));

parameter real carrier_freq = 1000000, ampl=1.0, offset = 1.0;

analog begin
    V(vdd,gnd) <+ 3.3;
    V(OUT_P,gnd) <+ 3.3;
    V(OUT_N,gnd) <+ 3.3;

    //Feed input sine
    V(SINE_IN,gnd) <+ ampl * sin(2.0*`M_PI*carrier_freq*$abstime);
    V(SINE_IN,gnd) <+ offset;
    // Tie the outputs to
    $bound_step(0.05/carrier_freq);
end

endmodule

I'm just getting started with using Verilog AMS for my designs so I apologies in advance if this question is ridiculously obvious to some. I feel I'm being stymied by my own inability to figure what exactly to google. 

  • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information