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Using $strobe in Verilog-A module

Brad RFeng

Hi,

I would like to observe voltages and currents in the Cadence supplied va module rfLib/lna during an sp analysis. The following lines were added in the analog block after the end of the initial_step block.
$strobe("V(in)=%e V(out)=%e I(in_int)=%e I(out_int)",V(in),V(out),I(in_int),I(out_int));
$strobe("a1=%e a2=%e",a1,a2);
The strings are displayed in the spectre.out window but all values are 0.0e+0. I was expecting to see the values change as the simulation iterations progressed. The module is simulating as expected and results returned to ADE output are correct. I'm relatively new to Verilog-A so perhaps I'm missing something basic? 

Regards,
Brad

  • in reply to ShawnLogan

    Thanks Shawn you've pulled the thread some more, all pulling of thread helps! I've discovered that the va compile step actually solves for the derivatives symbolically and I guess stores them away somewhere in memory in the form a Jacobian. This would eliminate the need for "hitting" the circuit with a couple voltages to extract the numeric derivatives. Unfortunately, this topic is not discussed in the Cadence Verilog-A LRM V21.1.pdf. Do you know of a more detailed document that goes into the theory of operation of Cadence Verilog-A?

    Brad

  • in reply to Brad RFeng

    Dear Brad RFeng,

    Brad RFeng said:
    I've discovered that the va compile step actually solves for the derivatives symbolically and I guess stores them away somewhere in memory in the form a Jacobian. This would eliminate the need for "hitting" the circuit with a couple voltages to extract the numeric derivatives. Unfortunately, this topic is not discussed in the Cadence Verilog-A LRM V21.1.pdf. Do you know of a more detailed document that goes into the theory of operation of Cadence Verilog-A?

    To be honest, I do not know of any other formal document other than the reference manual and occasional references in other manuals (such as the spectre RF Theory manual). However, what I have done in the past when I am puzzled about some aspect of a tool or its detailed operation is open an SR with Cadence to request the information. In a few cases where I did this, the Application Engineer with whom I worked created one or more documents to address the question and placed them on the Cadence support site for others to view. So, if you have the time and curiosity, you might consider opening a support vase with a few specific questions to start the conversation.

    Shawn

  • in reply to ShawnLogan

    , there is some coverage of what goes on in AC type analyses in The Designer's Guide to SPICE and SPECTRE.

    We don't generally cover the level of detail that you're asking for in the documentation, because that is all about the internal algorithms in the simulator. These, quite frankly, are not needed for users of the tools to do their job. Circuit simulators have to often linearise and solve - and a Verilog-A model is no different from a device model written in C/C++ (most compact models these days have their reference implementation in Verilog-A anyway).

    Andrew

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